A ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Chin, Shu-Yuan; Wu, Chung‐Yu

doi:10.1109/iscas.1993.393943

Cited by 4 publications

(6 citation statements)

References 14 publications

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“…Although both capacitor-ratio-independent technique and gainsensitivity reduction technique have been proposed, they have not yet been combined together to implement high-resolution A/D converters. In this work, an algorithm to reduce the sensitivities of both capacitor ratio and finite op-amp gain simultaneously is applied to the design of an algorithmic A/D converter [14]. Using this algorithm, the effective finite gain of the op-amps can be almost squared and the resolution of the algorithmic A/D converters can be independent of the capacitor ratio.…”

Section: Introductionmentioning

confidence: 99%

A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Chin

1996

IEEE J. Solid-State Circuits

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This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 m double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion.

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Section: Introductionmentioning

confidence: 99%

A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Chin

1996

IEEE J. Solid-State Circuits

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“…Primary nonideal effects in this structure include (1) capacitor mismatch, (2) opamp finite gain and offset, (3) parasitic capacitances, (4) clock feedthrough and charge injection, and (5) comparator offset. Well-known techniques can be used to overcome (3) and (4). Problems associated with (5) can be easily cancelled by using auto-zeroing, CDS, or digital redundancy (often referred to as digital correction) [5]- [6].…”

Section: Converter Structurementioning

confidence: 99%

“…Driven by the need for low-power and high-resolution data converters, a number of error-compensating techniques have been developed [1]- [4]. The key concept behind all these techniques is to manipulate the switching of capacitors ,which contain the signal charges (or other unit elements) in ways such that the randomly mismatched values will not affect the accuracy of the data conversion.…”

Section: Introductionmentioning

confidence: 99%

“…Most of these techniques also account for the input-referred offset voltages of the opamps used in the signal processing. And in the most recent work reported [4], the finite gain of the opamp is also compensated (effectively squaring the opamp gain) at the cost of many additional clock phases.…”

Section: Introductionmentioning

confidence: 99%

“…The most recent work also incorporating finite opamp gain compensation needs 7 clock periods per bit [4]. Thus, this new scheme is a significant improvement over existing implementations.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient error-cancelling algorithmic ADC

Zheng

Min

Moon

et al.

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in the applications which require low-cost medium-speed and high-resolution A/D conversion.

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An algorithmic analog-to-digital converter with low ratio- and gain-sensitivities 4N-clock conversion cycle

Chin

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

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A ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Cited by 4 publications

References 14 publications

A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Efficient error-cancelling algorithmic ADC

An algorithmic analog-to-digital converter with low ratio- and gain-sensitivities 4N-clock conversion cycle

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