A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Chin, Shu-Yuan; Wu, Chung‐Yu

doi:10.1109/4.508271

Cited by 20 publications

(3 citation statements)

References 18 publications

(21 reference statements)

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“…Nyquist Rate A/D Converters Flash A/D Converters [78][79][80][81] 6 bit 1 ⁄ f ck -Subranging and Pipeline A/D Converters [82][83][84][85][86] 12 bit < N ⁄ f ck = Folding A/D Converters [87][88] 10 bit < N ⁄ f ck -Successive Approximation A/D Converters [89][90][91][92] 12 bit N ⁄ f ck = Algorithmic A/D Converters [93][94][95] 12 bit N ⁄ f ck = Oversampled A/D Converters Dual-Slope A/D Converters [96][97] 20 bit 2 N+1 ⁄ f ck + Incremental A/D Converters [98][99][100] > 16 bit 2 N ⁄ f ck ++ Sigma-Delta A/D Converters [101][102][103][104][105][106][107][108][109][110][111][112][113][114][115][116][117][118] > 18 bit < 2 N ⁄ f ck ++…”

Section: Maximum Conversion Suitable For A/d Converter Architecture Rmentioning

confidence: 99%

Interface Circuitry and Microsystems

Malcovati

Maloberti

2006

Mems

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Sensing physical or chemical quantities is a fundamental task in information processing and control systems. A sensing element or transducer converts the quantity to be measured into an electrical signal, such as a voltage, a current, or a resistive or capacitive variation. The data obtained from the transducers then have to be translated into a form understandable by humans, computers, or measurement systems. An electronic circuit called a sensor interface usually performs this task. The functions implemented by a sensor interface can range from simple amplification or filtering to A/D conversion, calibration, digital signal processing, interfacing with other electronic devices or displays, and data transmission (through a bus or, recently, through a wireless connection, such as Bluetooth).Very-large-scale integration (VLSI) technologies have been extensively used to make sensor interface circuits since the appearance of the first integrated circuit (IC) in the early 1960s. Most of the sensor systems realized so far consist of discrete sensors combined with one or more application-specific integrated circuits (ASICs) or commercial components on a printed circuit board (PCB) or hybrid board. Over the past few years, however, progress in silicon planar technologies has allowed miniaturized sensors (microsensors) to be realized by exploiting the sensing properties of IC materials (silicon, polysilicon, aluminum, silicon oxide, and nitride) or additional deposited materials (such as piezoelectric zinc oxide, sensitive polymers, or additional metallization layers).When microsensors are realized using IC technologies and materials, it is possible to integrate the interface circuit and several sensors on the same chip or in the same package, leading to microsystems or micromodules. [1][2][3][4][5][6] The potential advantages of this approach are numerous: The cost of the measurement system is greatly reduced due to batch fabrication of both the sensors and the interface circuits; its size and interconnections are minimized; and its reliability is improved.

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Section: Maximum Conversion Suitable For A/d Converter Architecture Rmentioning

confidence: 99%

Interface Circuitry and Microsystems

Malcovati

Maloberti

2006

Mems

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“…1 [1][2][3][4][5][6][7][8][9][10]. As shown in Table 1, most of the ADCs are occupying a chip area exceeding 1.0 mm 2 and dissipate a power of several mW, although the performance can be considerably different depending on the actually employed CMOS technologies and the required specifications.…”

Section: Introductionmentioning

confidence: 99%

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

Kim

Lee

2009

Analog Integr Circ Sig Process

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This work proposes a 12 b 8 kS/s ultra-lowpower CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, lowpower, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature-and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 lm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm 2 consumes 16 lW at 8 kS/s and 2.5 V.

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“…Subranging, halfflash, and pipeline A/D converters need between two and N clock periods per conversion, with decreasing hardware complexity. At the beginning of each conversion cycle, switch S 1 is closed and the whole capacitive array is charged at the input voltage V in (precharge and [78][79][80][81] 6 bit 1 ⁄ f ck -Subranging and Pipeline A/D Converters [82][83][84][85][86] 12 bit < N ⁄ f ck = Folding A/D Converters [87][88] 10 bit < N ⁄ f ck -Successive Approximation A/D Converters [89][90][91][92] 12 bit N ⁄ f ck = Algorithmic A/D Converters [93][94][95] 12 bit…”

Section: A/d Convertermentioning

confidence: 99%