An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in the applications which require low-cost medium-speed and high-resolution A/D conversion.
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