Efficient error-cancelling algorithmic ADC

Abstract

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in the applications which require low-cost medium-speed and high-resolution A/D conversion.

A high-speed algorithmic ADC

“…This is due to the demand of high performance, portable and battery-powered equipment. It has been shown that, among the existing ADCs, the algorithmic ADC offers the advantages of both the circuit performance and small in size of chip area (Pouliquen et al 1991, Fong et al 1994, Signell et al 1997, Chang and Lee 1998, Zheng et al 2000, Quinn and Pribytko 2003. In addition, the N-bit resolution of an algorithmic ADC can be simply realized by cascading of N-bit cells.…”

“…For binary coding, the conversion technique requires the subtract function to generate a sawtooth-like waveform for a linearly increasing input signal. The current mode binary code algorithmic ADC has been proposed in literatures (Chang and Lee 1998, Zheng et al 2000, Quinn and Pribytko 2003. The configuration of these approaches is simple and can be realized with a minimum of chip area.…”