A low power high linearity phase interpolator design for high speed IO interfaces

Katare, Siddharth; Iyer, Sitaraman; Tong, Guluke; Munagala, Lasya R; Mahalingam, Nagarajan; Yang, Bangda

doi:10.1109/isocc.2014.7087577

Cited by 3 publications

(8 citation statements)

References 4 publications

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“…They are used in a variety of applications, e.g., clock-and data recovery (CDR) circuits [1], [2], for phase acquisition in phase-locked loops (PLL) [3], [4], phase ramp generator in sub-sampling PLLs [5]. A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay.…”

Section: Introductionmentioning

confidence: 99%

“…A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay. Several PI topologies have been proposed; Delay line based [6], [7], trigonometric [2], [8], [9], current-weighting [1], [3], [4], [10], [11], charge-steering [12] and constant-slope charging [5], [13].…”

Section: Introductionmentioning

confidence: 99%

“…When ΦIN1 or ΦIN2 goes low, the output capacitors are simultaneously charged through the two current sources. The propagation delay through unit A and C is given by (2), where VTH is the threshold voltage of the following stage.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Jakobsson

Serban²,

Gong³

2019

IEEE Trans. Circuits Syst. II

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Abstract-This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm 2 .

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Jakobsson

Serban²,

Gong³

2019

IEEE Trans. Circuits Syst. II

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“…Unlike the conventional methods to decrease fractional spurs in FNPLL [2][3][4], this Letter presents 45°input dithering to CMPI using the symmetrical error profile of the CMPI. The proposed 45°phase rotator block driven by pseudorandom binary sequence (PRBS) and digital compensation randomise the non-linearity error which is turned into white noise rather than periodic errors.…”

mentioning

confidence: 99%

“…Phase error in CMPI and fractional spurs: 7-bit CMPI produces a desired phase by adjusting IQ current weighting in a differential structure using 4-phase input signals (I, Q, IB, and QB), 32-bit weight control and 4-bit quadrant selection [1]. The CMPI-based fractional frequency with a linear CMPI code mapping leads to fractional spurs [3]. Fig.…”

mentioning

confidence: 99%

Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop

Ko¹,

Heo²,

Lee

et al. 2016

Electron. lett.

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A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45°offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45°p hase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.

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Orthogonal phase mixing for improved linearity phase interpolator

Sumesaglam

2022

Electronics Letters

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As the demand for high-speed low-power transceivers grows, it is critical to have precise clock timing circuits such as phase interpolators (PI) that allow maximizing link margin. A linearization technique which optimizes linearity without increasing power and area is presented. Implemented in a 7-nm complimentary metal oxide silicon (CMOS) technology, PI achieves less than 0.5 integral non-linearity (INL) while consuming only 184 μA from a 0.75-V supply at 4.3 GHz.

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A low power high linearity phase interpolator design for high speed IO interfaces

Cited by 3 publications

References 4 publications

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop

Orthogonal phase mixing for improved linearity phase interpolator

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