Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop

Ko, Jae-In; Heo, Minuk; Lee, J.; Kim, C.; Lee, M.

doi:10.1049/el.2016.2098

Cited by 1 publication

(3 citation statements)

References 6 publications

(19 reference statements)

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“…1 LSB of the PI is about 4-5 ps in a 3-4 GHz PLL, and its phase is ΔΣ-modulated to get low in-band noise. The inverter-based PI is adopted for less current consumption as compared to the current mode PI [27,28] that consumes the bias current and requires high supply for signal headroom. The PI phase and weight controller splits a large PI phase jump into several smaller jumps to prevent the glitches [27,28].…”

Section: B Fractional-n Divider With Pimentioning

confidence: 99%

“…The inverter-based PI is adopted for less current consumption as compared to the current mode PI [27,28] that consumes the bias current and requires high supply for signal headroom. The PI phase and weight controller splits a large PI phase jump into several smaller jumps to prevent the glitches [27,28]. The maximum phase jump at a time is limited to π/4 rad for no glitches, which leads to a maximum of 8 phase jumps per one reference cycle.…”

Section: B Fractional-n Divider With Pimentioning

confidence: 99%

“…The inverter-based PI consumes less power than the current-mode phase interpolator (CMPI), however, the poor linearity of the 32 inverter pairs has a significant effect on the PLL fractional spur. To improve the linearity of the PI, the PI 45⁰ phase dithering has been studied [28], but the fractional spur is still large, because the duty cycle distortion of the DIV2 can directly affects the 4 quadrants for the PI. Therefore, in this PLL, the PI nonlinearity for whole PI phases is digitally calibrated.…”

Section: Pi Nonlinearity Calibrationmentioning

confidence: 99%

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A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

et al. 2022

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This paper presents analyses of jitter and reference spur of a digital PLL using a phasefrequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (<30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply.INDEX TERMS Time amplifier (TA), digitally controlled oscillator (DCO), digital phase-locked loop (PLL), PLL jitter analysis, reference spur, phase interpolator (PI) nonlinearity calibration.

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