A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45°offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45°p hase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.
A gain controllable SR-latch-based time difference amplifier (TDA) with a gain of up to 150 by controlling the regeneration time constant, especially with programmable transconductance (g m), is presented. The presented g m control uses resistor degeneration at the input switches so that the effective g m is reduced, whereas the time difference gain increases. Unavoidable large crowbar current from the slow regeneration is avoided by shifting to the fast regeneration mode after regeneration is completed, which effectively reduces current consumption by 29.3%.
This paper presents analyses of jitter and reference spur of a digital PLL using a phasefrequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (<30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply.INDEX TERMS Time amplifier (TA), digitally controlled oscillator (DCO), digital phase-locked loop (PLL), PLL jitter analysis, reference spur, phase interpolator (PI) nonlinearity calibration.
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