Low‐power programmable high‐gain time difference amplifier with regeneration time control

Abstract

A gain controllable SR-latch-based time difference amplifier (TDA) with a gain of up to 150 by controlling the regeneration time constant, especially with programmable transconductance (g m), is presented. The presented g m control uses resistor degeneration at the input switches so that the effective g m is reduced, whereas the time difference gain increases. Unavoidable large crowbar current from the slow regeneration is avoided by shifting to the fast regeneration mode after regeneration is completed, which effectively reduces current consumption by 29.3%.

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

“…From Section IV, to suppress the reference spur by the mismatches, the TA has to achieve high-gain, such as over 100. In this PFD-TA PLL, the latch-based TAs in [21,29,39] are exploited where the regeneration core consists of an input delay, a SR latch and an XOR, as shown in Fig. 7.…”

“…7(a), the delay cell, 𝑇 𝑜𝑓𝑓 , on one input of each SR latch makes the time-amplifying characteristic between −𝑇 𝑜𝑓𝑓 and 𝑇 𝑜𝑓𝑓 [39]. With 𝑅 𝑀𝑂𝑆 control in the SR latch, the TA can achieve gain over 100, but the high-gain causes the long regeneration time unavoidably, which incurs large crowbar current in the latch cores, and the core output capacitor also leads to significant power consumption from the charging and discharging cycle [29].…”