Standard cell libraries are an integral part of converting an RTL to a manufacturable physical design. The automatic place and route EDA tools use these characterized standard cell libraries to arrive at an optimal design within given constraints. The correlation between characterized data and the actual behaviour of cells on Silicon is critical for meeting the desired performance of the manufactured chip. In this paper, we present a modular design and measurement method which can be implemented in an ASIC for correlating the characteristics of the standard cell library. This method simplifies the design of the package and the test board and relatively simple test equipment can be used to measure the silicon characteristics. The ASIC presented in this paper was designed in 180nm for characterizing standard cells, which are delivered as part of the foundry design kit.
The knowledge of power supply noise profile in microprocessors can facilitate in improving the performance significantly. In the deep sub-micron process employing ondie voltage regulators to convert incoming higher voltage from motherboard to lower core voltage supply, the measurement of input voltage profile becomes further challenging. Voltage to frequency conversion is often used to convert local supply voltage to it's corresponding digital value. The state-of-art solutions rely on low impedance voltage divider to generate acceptable voltage which modulates the frequency of voltage controlled oscillator (VCO). In this paper we present a novel high voltage compliant ring oscillator which can replace existing low voltage VCO and can perform with similar accuracy as state-of-art solutions.
In this paper, we present 3 novel methods for generating voltage references. The first architecture focuses on low voltage high precision voltage reference reducing the variation to 5mV from 105mV across temperature of -40 to 100°C. The second architecture focuses on low voltage low power reference bringing down current consumption to half. The third one is a hybrid architecture with lesser voltage reference variation and lesser power consumption but has higher operational voltage.
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