Orthogonal phase mixing for improved linearity phase interpolator

Abstract

As the demand for high-speed low-power transceivers grows, it is critical to have precise clock timing circuits such as phase interpolators (PI) that allow maximizing link margin. A linearization technique which optimizes linearity without increasing power and area is presented. Implemented in a 7-nm complimentary metal oxide silicon (CMOS) technology, PI achieves less than 0.5 integral non-linearity (INL) while consuming only 184 μA from a 0.75-V supply at 4.3 GHz.