A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Abstract

Abstract-This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm 2 .

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

“…On the contrary, clock phase interpolation methods offer a solution for producing a multiplied frequency with significantly reduced lock/settle time, less power consumption, and smaller silicon area [14]. These methods, therefore, considerably reduce the overall cost of the design and accelerate time-to-market for new designs [15]. Since the clock multipliers in this category are generally digital intensive, it is very convenient to make them portable among different processes.…”

All Digital CMOS 5-BIT Phase Interpolator at 10 Gigahertz in 65NM Technology

“…The n term represents the desired interpolation weighting factor, which can be any number between 0 and N. (red and blue, respectively) being mixed equally using an even weighted interpolation to achieve an output signal, 𝜃 (green), that has a phase exactly between the two input phases. From figure 2.2., the mid-point of the output signal's high to low transition occurs exactly between the midpoints of that of the two input signals [14]. It is important to note, the input signals that are shown here are non-overlapping and linear interpolation requires overlapping clock signals.…”