This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19% to 68%. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1% power and 28% area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 µW for Bluetooth LE demodulation and 225 µW for LoRa preamble detection (BW = 500 kHz, SF = 11).

The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-intime translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.

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