Fast Cycle-Accurate Compiled Simulation

Přikryl, Zdeněk; Hruška, Tomáš; Masařík, Karel; Husár, Adam

doi:10.3182/20101006-2-pl-4019.00016

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…Therefore, the basic type of compiled simulator cannot simulate SMC and it is dependent on the analyzed application. Note that this is not true in the case of dynamic compiled simulators [15].…”

Section: State Of the Artmentioning

confidence: 93%

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Fast just-in-time translated simulator for ASIP design

Přikryl

Křoustek

Hruška

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-intime translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.

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Section: State Of the Artmentioning

confidence: 93%

“…The basic type of simulator is an interpreted [15] or compiled simulator [16]. The run of interpreted simulator is based on the following concept.…”

Section: State Of the Artmentioning

confidence: 99%

Fast just-in-time translated simulator for ASIP design

Přikryl

Křoustek

Hruška

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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show abstract

“…Intel's 8051 [28]), while the instruction is encoded in a different order. An example of operations and groups can be found in [21], [17] and in the following sections.…”

Section: The Isac Languagementioning

confidence: 99%

“…If the developer wants to increase the speed of a simulation, he or she can use the second type of simulator, the compiled simulator [21]. It is created in two steps.…”

Section: A Different Types Of Simulatorsmentioning

confidence: 99%

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Přikryl¹,

Křoustek²,

Hruška³

et al. 2011

JoC

Self Cite

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Most of modern embedded systems for multimedia and network applications are based on parallel data stream processing. The data processing can be done using very long instruction word processors (VLIW), or using more than one high performance application-specific instruction set processor (ASIPs), or even by their combination on single chip. Design and testing of these complex systems is time-consuming and iterative process. Architecture description languages (ADLs) are one of the most effective solutions for single processor design. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in nowadays ADLs. This article presents utilization of new extensions for existing architecture description language ISAC. These extensions are used for easy and fast prototyping and testing of parallel based systems and processors.

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Register file management for PRET machines

Košt'ál

Sójka

2021

Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis

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Fast Cycle-Accurate Compiled Simulation

Cited by 3 publications

References 3 publications

Fast just-in-time translated simulator for ASIP design

Fast just-in-time translated simulator for ASIP design

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Register file management for PRET machines

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