Fast just-in-time translated simulator for ASIP design

Přikryl, Zdeněk; Křoustek, Jakub; Hruška, Tomáš; Kolář, Dušan

doi:10.1109/ddecs.2011.5783094

Cited by 6 publications

(8 citation statements)

References 7 publications

(5 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(2) In the operation part, processor instruction set (i.e., assembler language syntax, binary encoding, and behavior of each instruction) is specified. ISAC is, for example, used for ASIP design and automatic generation of a complete toolchain-C/C++ compiler [23], several simulator types [24], multi-level debugger [25], etc.…”

Section: Lissom Project's Retargetable Decompilermentioning

confidence: 99%

Detection and Recovery of Functions and their Arguments in a Retargetable Decompiler

Durfina

Křoustek

et al. 2012

2012 19th Working Conference on Reverse Engineering

Self Cite

View full text Add to dashboard Cite

Detection and recovery of high-level control structures, such as functions and their arguments, plays an important role in decompilation. It has a direct impact on the quality of the generated code because it is needed for generating functionally equivalent and highly readable code. In this paper, we present an innovative, platform-independent method of detection and recovery of functions and their arguments. This method is based on static code interpretation and iterative bidirectional search over reconstructed basic blocks. This approach has been adopted and tested in an existing retargetable decompiler. According to our experimental results, the proposed retargetable solution is fully competitive with existing hand-coded decompilers.

show abstract

Section: Lissom Project's Retargetable Decompilermentioning

confidence: 99%

Detection and Recovery of Functions and their Arguments in a Retargetable Decompiler

Durfina

Křoustek

et al. 2012

2012 19th Working Conference on Reverse Engineering

Self Cite

View full text Add to dashboard Cite

show abstract

“…Greedy cycles from the state diagram we can determine optimal latency cycles which result in the MAL. There are infinitely many latencies cycles, one can from state diagram, suppose that (1,12), (1,4,6,8,10,12), (4,6), (4,6,8)…… are legitimate cycles traced from the state diagram. As simple cycles are latency cycles in which each state appear only ones.…”

Section: B Application Specific Latency Predictionmentioning

confidence: 99%

“…Only (4), (6), (8), (6,8), (10,12) are simple cycles the cycles (6,12,10,12) are a complex cycle because of its travels these the states (101010101110) twice or more. Similarly (4,6,4,6,8,6) is not simple it repeats the state so we need greedy cycles is one whose edge are all made with minimum latencies from their respective starting states. The greedy cycles (1, 12) average latency is 6.5, which is lower than that of the simple cycle (10, 12) is 11[ Fig.…”

Section: B Application Specific Latency Predictionmentioning

confidence: 99%

“…The FPGA based emulator is alternative to pure software cycle-accurate simulation and this tool chain to reduce the design exploration time [13]. Fast and accurate processor simulator used for high performance ASIP simulation [4] and an integrated tool chain design also evaluated for ASIP systems [5]. ASIP architecture also design for a Discrete Fourier transform (DFT)/Discrete cosine transform (DCT) /Finite impulse response filters (FIR) engine [14].…”

mentioning

confidence: 99%

See 1 more Smart Citation

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

Khatwal¹,

Jain²

2016

ijacsa

View full text Add to dashboard Cite

Abstract-Low power embedded system requires effective memory design system which improves the system performance with the help of memory implementation techniques. Application specific data allocation design pattern implements the memory storage area and internal cell design techniques implements data transition speeds. Embedded cache design is implemented with simulator and scheduling approaches which can reduce the cache miss behavior and improve the cache hit quantities. Cache hit optimization, delay reduction and latency prediction techniques are effective for ASIP design. The design functionality is simply specifying the tradeoff among various design metrics like performance, power, size, cost and flexibility. ASIP behavior and memory storage area optimized for low power embedded system and implements cycle time with effective scheduling techniques which implements the system performance with low power consumption.

show abstract

“…Each simulator type suites for a different usage, see [12,13] for details. The debugger allows dynamic analysis on the different levels (e.g.…”

Section: Figmentioning

confidence: 99%

Approaching Retargetable Static, Dynamic, and Hybrid Executable-Code Analysis

Křoustek¹,

Kolář²

2013

AIP

View full text Add to dashboard Cite

Abstract:Program comprehension and reverse engineering are two large domains of computer science that have one common goal -analysis of existing programs and understanding their behaviour. In present, methods of source-code analysis are well established and used in practice by software engineers. On the other hand, analysis of executable code is a more challenging task that is not fully covered by existing tools. Furthermore, methods of retargetable executable-code analysis are rare because of their complexity. In this paper, we present a complex platform-independent toolchain for executable-code analysis that supports both static and dynamic analysis. This toolchain, developed within the Lissom project, exploits several previously designed methods and it can be used for debugging user's applications as well as malware analysis, etc. The main contribution of this paper is to interconnect the existing methods and illustrate their usage on the real-world scenarios. Furthermore, we introduce a concept of a new retargetable method -the hybrid analysis. It can eliminate the shortcomings of the static and dynamic analysis in future.

show abstract

Fast just-in-time translated simulator for ASIP design

Cited by 6 publications

References 7 publications

Detection and Recovery of Functions and their Arguments in a Retargetable Decompiler

Detection and Recovery of Functions and their Arguments in a Retargetable Decompiler

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

Approaching Retargetable Static, Dynamic, and Hybrid Executable-Code Analysis

Contact Info

Product

Resources

About