A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

Amor, Hela Belhadj; Bernier, Carolynn; Přikryl, Zdeněk

doi:10.1109/tc.2021.3063027

Cited by 20 publications

(16 citation statements)

References 31 publications

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“…However, IoT devices face the challenges of the shortage of computing, memory and energy resources. In recent years, several custom RISC-V instruction set extensions have been proposed to reduce the energy consumption of floating-point computation [40] of IoT devices, and improve the efficiency of digital signal processing (DSP) [5], [15].…”

Section: A Internet Of Thingsmentioning

confidence: 99%

“…This scheme is superior to the traditional scheme in terms of computing time and power consumption. Amor et al [5] concentrate on the acceleration of complicated physicallayer wireless DSP algorithms (e.g., FFT computation, gain control) used in IoT. They proposed an extension including complex arithmetic instructions, reconfigurable multiplication instructions and automatic gain control instructions, to reduce the number of cycles required by DSP algorithms and reduce energy consumption.…”

Section: A Internet Of Thingsmentioning

confidence: 99%

“…In addition to the instruction set extension standards developed by the standard organization, academic researchers have also carried out a number of studies to customize instruction set extensions for a variety of scenarios to accelerate specific applications or computing tasks. For instance, work [5] proposed a DSP instruction set extension for Internet of Things applications to improve the energy efficiency of wireless signal processing. For artificial intelligence applications, works [6] and [7] proposed instruction set extensions for acceleration of deep learning algorithms.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: A Internet Of Thingsmentioning

confidence: 99%

Section: A Internet Of Thingsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…A 64-bit high-performance embedded RISC-V processor with SIMD extensions is designed, and its performance is comparable (i.e., within 20% on most benchmarks) with ARM Cortex-A73. In article [ 24 ] the authors propose an ISA extension for DSP (Digital Signal Processors) processing in IoT devices with power consumption constraints. The reported speedups are over 50% for the FFT algorithm with an area overhead of 28% compared to the RI5CY implementation of RISC-V.…”

Section: Related Workmentioning

confidence: 99%

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

Popovici

Stan

2023

Micromachines

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Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using low-cost and reliable setups. In the context of RISC-V Extensions and Domain-Specific Architecture, this paper proposes a Real-Time RISC-V-based CAN-FD Bus Diagnosis Tool, named RiscDiag CanFd, as an open-source alternative. The RISC-V Core extension is a CAN-FD Communication Unit controlled by a dedicated ISA Extension. Besides the extended RISC-V core, the proposed SoC provides UDP Communication via Ethernet for connecting the proposed solution to a PC. Additionally, a GUI application was developed for accessing and using the hardware solution deployed in an FPGA. The proposed solution is evaluated by measuring the lost frame rate, the precision of captured frames timestamps and the latency of preparing data for Ethernet communication. Measurements revealed a 0% frame loss rate, a timestamp error under 0.001% and an acquisition cycle jitter under 10 ns.

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“…In [80], Amor et al define a RISC-V ISA (RV32IM) extension for ultra-low power software-defined wireless IoT transceivers. The authors add 14 custom instructions tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations.…”

Section: Related Workmentioning

confidence: 99%

IXIAM: ISA EXtension for Integrated Accelerator Management

et al. 2023

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During the last years, hardware accelerators have been gaining popularity thanks to their ability to achieve higher performance and efficiency than classic general-purpose solutions. They are fundamentally shaping the current generations of Systems-on-Chip (SoCs), which are becoming increasingly heterogeneous. However, despite their diffusion, a standard, general solution to manage them while providing speed and consistency has not yet been found. Common methodologies rely on OS mediation and a mix of user-space and kernel-space drivers, which can be inefficient, especially for fine-grained tasks. This paper addresses these sources of inefficiencies by proposing an ISA eXtension for Integrated Accelerator Management (IXIAM), a cost-effective HW-SW framework to control a wide variety of accelerators in a standard way, and directly from the cores. The proposed instructions include reservation, work offloading, data transfer, and synchronization. They can be wrapped in a high-level software API or even integrated into a compiler. IXIAM features also a user-space interrupt mechanism to signal events directly to the user process. We implement it as a RISC-V extension in the gem5 simulator and demonstrate detailed support for complex accelerators, as well as the ability to specify sequences of memory transfers and computations directly from the ISA and with significantly lower overhead than driver-based schemes. IXIAM provides a performance advantage that is more evident for small and medium workloads, reaching around 90¢ in the best case. This way, we enlarge the set of workloads that would benefit from hardware acceleration.

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A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

Cited by 20 publications

References 31 publications

RISC-V Instruction Set Architecture Extensions: A Survey

RISC-V Instruction Set Architecture Extensions: A Survey

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

IXIAM: ISA EXtension for Integrated Accelerator Management

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