RISC-V Instruction Set Architecture Extensions: A Survey

Cui, Enfang; Li, Tianzheng; Qian, Wei

doi:10.1109/access.2023.3246491

Cited by 26 publications

(10 citation statements)

References 57 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2. Different combi- [20], [21], and allows the addition of specific custom instructions, as in [22]. Since 2010, five basic instruction sets (RVWMO, RV32I, RV32E, RV64I, and RV128I) and 21 different feature extensions, including the V extension [23] and the draft cryptography extension [24], have been released.…”

Section: B Risc-v and The Packed Simd Extensionmentioning

confidence: 99%

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Yu,

Yuan,

Chen

et al. 2024

IEEE Access

View full text Add to dashboard Cite

In recent years, considerable research has focused on the use of custom hardware to accelerate deep learning on edge devices. However, the end-to-end flow of deep learning includes preprocessing and postprocessing. Deep learning hardware accelerators cannot accelerate these operations, which consequently becomes a performance bottleneck in the execution flow. In this study, we propose optimization methods to improve preprocessing and postprocessing at the edge devices. For this purpose, we adopt Tensor Virtual Machine (TVM), an end-to-end machine learning compiler framework. TVM provides hybrid script, which is a frontend language that allows users to write programs for preprocessing and postprocessing. We propose rewriting strategies to improve the performance of operators written in hybrid script through the RISC-V Packed SIMD extension (P extension). RISC-V is an open instruction set architecture (ISA) that provides base instructions and many extensions for different use cases. The P extension defines specific subword single-instruction multiple-data (SIMD) instructions that allow complex computations to be efficiently performed on edge devices. In this study, we design custom instructions based on the RISC-V P extension for rewriting strategies to accelerate deep learning operations. Experimental results indicate that our methods improve performance by a factor of 1.28 to 15.29.

show abstract

Section: B Risc-v and The Packed Simd Extensionmentioning

confidence: 99%

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Yu,

Yuan,

Chen

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…This design methodology enables developers to customise RISC-V processors to meet the specific needs of their applications, making them appropriate for a wide range of computing devices. The European Processor Initiative has adopted RISC-V for designing and manufacturing supercomputing CPUs [2].…”

Section: Basic Theory Of Risc-v and Its Development Prospectmentioning

confidence: 99%

“…RISC-V has a wide range of applications thanks to its versatility and flexibility. These applications include low-power embedded devices, high-performance computation, computer security, and machine learning [1][2][3]. It is likely that RISC-V's influence on the global chip industry, as well as the wider technological environment, will increase as it continues to flourish [3].…”

Section: Introductionmentioning

confidence: 99%

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

Deng

2024

ACE

View full text Add to dashboard Cite

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

show abstract

“…There are fields such as Internet of Things (IoT) [1], [2], cybersecurity [3], [4], domain-specific processor [5], [6], etc., where one works directly with assembly code on real hardware rather than with high-level languages [7].…”

Section: Introductionmentioning

confidence: 99%

CREATOR: An Educational Integrated Development Environment for RISC-V Programming

Camarmas-Alonso,

Garcia-Carballeira,

Calderon-Mateos

et al. 2024

IEEE Access

View full text Add to dashboard Cite

This article introduces a new integrated development environment called CREATOR (didaCtic and geneRic assEmbly progrAmming simulaTOR) that provides an interactive platform for educational assembly programming. CREATOR is specially designed for the academic environment, so it is very intuitive to users who are encountering assembly for the first time. It makes the traditional theory classes interactive, engaging students' participation. Moreover, it is a multiplatform simulator that can be used with a web browser without requiring a server or additional installations, and it can be used on different types of devices. CREATOR allows all the necessary steps to be performed on the same tool, from the implementation of the assembly program to its execution on real hardware. For this purpose, it allows editing, compiling, simulating, debugging, and loading the program on the hardware device without auxiliary software. In addition, it is also capable of detecting compilation errors, execution errors, and violations of the parameter passing convention, helping users understand the reason for a given error so that they can resolve it. CREATOR offers the RISC-V and MIPS32 architectures by default. However, it is possible to modify these architectures or add new architectures in the tool as needed by any user. This feature allows teachers to prepare practical labs adapted to the teaching objectives, and it can also be used for research, e.g., for the study of different instruction sets. INDEX TERMSAssembly programming, educational simulator, ESP32-RISCV, integrated development environment (IDE), RISC-V.

show abstract

RISC-V Instruction Set Architecture Extensions: A Survey

Cited by 26 publications

References 57 publications

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

CREATOR: An Educational Integrated Development Environment for RISC-V Programming

Contact Info

Product

Resources

About