ICM 2011 Proceeding 2011
DOI: 10.1109/icm.2011.6177413
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Retargetable multi-level debugging in HW/SW codesign

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Cited by 3 publications
(5 citation statements)
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“…(2) In the operation part, processor instruction set (i.e., assembler language syntax, binary encoding, and behavior of each instruction) is specified. ISAC is, for example, used for ASIP design and automatic generation of a complete toolchain-C/C++ compiler [23], several simulator types [24], multi-level debugger [25], etc.…”
Section: Lissom Project's Retargetable Decompilermentioning
confidence: 99%
“…(2) In the operation part, processor instruction set (i.e., assembler language syntax, binary encoding, and behavior of each instruction) is specified. ISAC is, for example, used for ASIP design and automatic generation of a complete toolchain-C/C++ compiler [23], several simulator types [24], multi-level debugger [25], etc.…”
Section: Lissom Project's Retargetable Decompilermentioning
confidence: 99%
“…The platform-specific analysis of executables is a partially solved problem, because implementation of such tool is a straightforward task [8,15]. The existing toolchains usually contain both dynamic and static tools.…”
Section: State Of the Artmentioning
confidence: 99%
“…In other projects (ArchC, Sim-nML, EXPRESSION, LISA, etc), the situation is very similar -they support various types of automatically-generated simulators and debuggers, but the static analysis is very limited [8].…”
Section: State Of the Artmentioning
confidence: 99%
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