Falls are a serious medical and social problem among the elderly. This has led to the development of automatic fall-detection systems. To detect falls, a fall-detection algorithm that combines a simple threshold method and hidden Markov model (HMM) using 3-axis acceleration is proposed. To apply the proposed fall-detection algorithm and detect falls, a wearable fall-detection device has been designed and produced. Several fall-feature parameters of 3-axis acceleration are introduced and applied to a simple threshold method. Possible falls are chosen through the simple threshold and are applied to two types of HMM to distinguish between a fall and an activity of daily living (ADL). The results using the simple threshold, HMM, and combination of the simple method and HMM were compared and analyzed. The combination of the simple threshold method and HMM reduced the complexity of the hardware and the proposed algorithm exhibited higher accuracy than that of the simple threshold method.

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A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.

A surface potential-based low-field drain current compact model is presented for twodimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect transistors that takes into account the effect of interface trap states on device current-voltage (I ds -V gs ) characteristics and transconductance g m . The presence of interface trap states detrimentally affects device I ds -V gs performance. Minimal work exists on the extraction of trap states (cm −2 eV −1 ) of MoS 2 /high-K dielectric/metal-gate stacks. Additionally, there is a lack of compact models for 2D TMD MOSFETs that can take into account the effect of trap states on device I ds -V gs performance. This study presents a method to extract the interface trap distribution of MoS 2 MOSFETs using a compact model. Presented as part of the model is a surface potential/ interface trap charge self-consistent calculation procedure and a drain current expression that does not need numerical integration. The model is tested against reported experimental I ds -V gs data, and excellent agreement is found between the experiment and the model.

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