Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

Najam, Faraz; Yu, Yun Seop; Cho, Keun Hwi; Yeo, Kyongmin; Kim, Dong-Won; Hwang, Jiwon; Kim, Sansig; Hwang, Sung Woo

doi:10.1109/ted.2013.2268193

Cited by 19 publications

(21 citation statements)

References 34 publications

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“…In some of these reports analytical models have been used for extracting the Dit in FD-SOI MOSFETs [10], [11]. Also in the field of GAA Si nanowire FETs analytical models have been used with [12], [13] or without [14] the aid of numerical simulation tools.…”

Section: Ilialmentioning

confidence: 99%

Interface trap density estimation in FinFETs from the subthreshold current

Schmitz

Kaleli

Kuipers

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is hased on the precise determination of the gate voltage dependent ideality factor of the suhthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.

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Section: Ilialmentioning

confidence: 99%

Interface trap density estimation in FinFETs from the subthreshold current

Schmitz

Kaleli

Kuipers

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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“…These degradations will consequently increase device power consumption . Furthermore, the reported experimental subthreshold swing (SS) values for long‐channel surrounding gate silicon nanowire (Si‐NW) FETs are found to be much beyond the ideal value of 60 mV/decade . Because the long‐channel transistors do not show subthreshold degradation induced by short‐channel effects , the interface traps may be the dominant cause of SS degradation for long‐channel Si‐NW FETs .…”

Section: Introductionmentioning

confidence: 99%

A surface‐potential‐based model for silicon nanowire junctionless field‐effect transistors including interface traps

Deng

Fan

Han

et al. 2014

Int J Numerical Modelling

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Interface trap is directly related to the electrical characteristics and reliability of the transistor, and it is an important factor affecting the performance of the device. This paper presents an analytic surface-potential-based model for cylindrical silicon nanowire junctionless field-effect transistors (Si-NW JLFET) including interface traps. In this paper, the proposed model is applicable to all Si-NW JLFET working region including different interface trap charges with several nanowire radii and doping concentrations. Simulation results show that interface trap charges present two properties (positive or negative) depending on the different positions of the Fermi level in band gap, which have a significantly influence on the surface potential to cause junctionless transistor subthreshold degradation and flatband shifting. In addition, appropriate device parameters can effectively reduce the impact to the characteristic of the device made by the interface trap without degrading the performance of device. Copyright

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“…However, in this work, instead of fitting Q it in a drain current expression, a thorough analytical framework has been developed, based on fundamental MOGFET device physics, to extract important experimental parameters including Q it , C it and φ s data from experimental C tot – V gs data as highlighted in the section “Experimental φ s , C it , and Q it extraction”. Using these experimental parameters as a reference and the framework developed earlier [14–15] an analytical framework was presented to extract the interface trap distribution of MOGFET devices.…”

Section: Resultsmentioning

confidence: 99%

“…8 using Q it_calc and φ s_calc as input variables. The self-consistent C it_calc –φ s_calc calculation procedure is based on our earlier works on MOSFET interface trap drain current modeling [14–15]. The procedure is highlighted in Fig.…”

Section: Basic Equations and Parametersmentioning

confidence: 99%

Metal oxide-graphene field-effect transistor: interface trap density extraction model

Najam

Lau

Lim

et al. 2016

Beilstein J. Nanotechnol.

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SummaryA simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship I ds–V gs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage C tot–V gs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

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Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

Cited by 19 publications

References 34 publications

Interface trap density estimation in FinFETs from the subthreshold current

Interface trap density estimation in FinFETs from the subthreshold current

A surface‐potential‐based model for silicon nanowire junctionless field‐effect transistors including interface traps

Metal oxide-graphene field-effect transistor: interface trap density extraction model

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