A surface potential-based low-field drain current compact model is presented for twodimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect transistors that takes into account the effect of interface trap states on device current-voltage (I ds -V gs ) characteristics and transconductance g m . The presence of interface trap states detrimentally affects device I ds -V gs performance. Minimal work exists on the extraction of trap states (cm −2 eV −1 ) of MoS 2 /high-K dielectric/metal-gate stacks. Additionally, there is a lack of compact models for 2D TMD MOSFETs that can take into account the effect of trap states on device I ds -V gs performance. This study presents a method to extract the interface trap distribution of MoS 2 MOSFETs using a compact model. Presented as part of the model is a surface potential/ interface trap charge self-consistent calculation procedure and a drain current expression that does not need numerical integration. The model is tested against reported experimental I ds -V gs data, and excellent agreement is found between the experiment and the model.
The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.
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