Axial p–n Nanowire Gated Diodes as a Direct Probe of Surface-Dominated Charge Dynamics in Semiconductor Nanomaterials

Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

“…The boron-doped p-type Si NWs used in this study were synthesized using a nanocluster-catalyzed vapor-liquid-solid transport method in a low-pressure chemical vapor deposition reactor with a silane (SiH 4 ) to diborane (B 2 H 6 ) gas ratio of 5,500:1. This synthesis procedure is described in detail elsewhere [ 11 ]. Single-crystal Si NWs with a typical diameter of 50–70 nm were first dispersed by ultrasonication in isopropanol and then transferred onto a substrate by dropping a liquid suspension of Si NWs using a pipette.…”

“…Source and drain electrodes were patterned by photolithography followed by electron-beam evaporation of 80 nm Ni and 50 nm Au electrode on a Si NW to form Ohmic contact between NWs and electrodes, along with a lift-off process. Before the electrode deposition, Si NWs were etched in a 1 % hydrofluoric acid solution for 15 s to remove a native oxide layer on the shell of the NWs [ 11 ]. The 200 nm thick P(VDF-TrFE) ferroelectric layer was prepared by mixing P(VDF-TrFE) at 0.08 wt% in 2-butanone.…”

Realization of high performance ferroelectric-gate FET nonvolatile memory using p-type Si nanowire channel

“…The boron-doped p-type Si NWs used in this study were synthesized by the nanocluster-catalyzed VLS method in a low pressure chemical vapor deposition reactor that was reported in detail as cited elsewhere [3] . Single crystal Si NWs with a typical diameter of 50-70nm were transferred onto a heavy doped p-type silicon substrate as a back gate with a 100nm thick thermal oxide layer on top as a gate oxide layer.…”

“…Source and drain electrodes were patterned by photolithography followed by electron-beam evaporation of 80nm Ti/50nm Au electrodes on a Si NW. Right before electrode deposition, Si NWs were etched in a 1% hydrofluoric acid solution in 15sec to remove the native oxide layer on the shell of the nanowires [3] . The 200nm thick P(VDF-TrFE) ferroelectric layer was prepared by mixing P(VDF-TrFE) at 0.08wt% in a solvent 2-butanone.…”

Silicon nanowires: electron holography studies of doped p–n junctions and biased Schottky barriers

“…In working towards the design of SiNW heterostructures with more sophisticated band-engineering, much work has been conducted on the properties of individual SiNWs by means of microscopy, spectroscopy and charge-transport techniques, where no contact is needed or only simple Ohmic contacts are required [1][2][3]. Further work has similarly investigated junctions of nanowires with p-type and n-type doping explicitly fabricated by controlled synthesis techniques [6][7][8][9]. For other purposes that intentionally utilize the potential barrier at a metal-Si interface, special attention has been paid to characterize the electrical properties of such junctions [10][11][12].…”