An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Timing jitter as a key performance of single-photon avalanche diode (SPAD) detectors plays a significant role in determining the fast temporal response behavior of the SPAD device. Nevertheless, few analytic models are developed to directly calculate the characteristic of timing jitter for its modeling difficulty. In this paper, we propose a simple analytic modeling method, which can predict the temporal response of SPADs, without using time-consuming Monte Carlo simulation. Model investigation incorporates avalanche current, avalanche buildup time, and jitter tail under different conditions. Furthermore, the key model parameters provided by Geiger mode technology computer-aided design simulation allow an accurate prediction on timing jitter. Analytical results indicate that for an SPAD device structure with a shallow P+/N-well junction in a 0.18-μm CMOS technology, the Gaussian peak response with about 110-ps full-width at half-maximum and the exponential jitter tail are in good agreement with the measured data, validating the accuracy, and feasibility of this modeling method. INDEX TERMS Single photon avalanche diodes (SPADs), timing jitter, analytic model, jitter tail.

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Al2O3/GeOx/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 1011 cm−2 eV−1 have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al2O3 with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al2O3 is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al2O3 network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

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