An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

Abstract

An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

Towards bendable CMOS magnetic sensors

“…The structure in Figure 2 is biased by a current I S =1 mA applied along [100] Si-direction and the Hall voltage V H in the transversal direction [010] is recorded. The simulation results show that the current-related sensitivity in the flat state is S I ∼ =71 V/AT, which is in agreement with [18].…”

“…Since a Hall sensor is both magnetic-and stress-sensitive, it can be used in both cases. However, in order to determine accurately the magnetic field strength when the sensor is deformed mechanically, the piezoresistive effect [17] must be compensated, [13], [18].…”

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

“…When a voltage V or current I bias is supplied via one pair of terminals and a perpendicular magnetic field B Z is applied to the device surface, the Hall voltage V H appears on the other pair of terminals due to the Hall effect. Considering the geometry of a real Hall plate, V H can be expressed with the current related sensitivity S I [13]: $V_H=S_I {\mathrm{italicIB}}_Z,$with $S_I=G{\mu }_H R_{\mathit{square}}=\frac{G\cdot r_H}{{\mathrm{italicqn}}_{\mathit{NW}} t_{\mathit{NW}}}$. S I is determined by the geometrical correction factor G , the Hall mobility μ H or the Hall factor r H , the doping concentration n NW of the N-well, and the effective depth of the N-well t NW .…”

Single-Chip Integrated 3-D Hall Sensor

“…Horizontal Hall piece is used in direction Z. Fig.2 shows thestructure of the distributed and combined 3-D Hall unit, the design of the horizontal device of which already exists [5,6] and the vertical devices will be connected parallel. The advantages of this structure are that the Hall offset voltage is small and that the follow-up signal conditioning circuit is relatively simple.…”

“…Fig.1 shows the working principle of the single-chip CMOS 3-D Hall magnetic sensor with the 3-D Hall sense unit (the scale of sense unit is amplified). 3-D magnetic sense unit is within 100um*100um in 0.18 m high-voltage complementary metal-oxide semiconductor technology [5,6]. It can accurately measure the relative distance and position between the source of the magnetic field and the chip.…”