A monoamine–dithiol mixture is used to prepare homogeneous Cu(In, Ga)Se2 (CIGSe) molecular precursor solution, which yields a highly sulfur depleted CIGSe thin-film solar cell with a power conversion efficiency of 12.2%.
Solution processing of metal chalcogenides using elemental metals dissolved in an amine–thiol solvent mixture has recently received a great deal of attention for the fabrication of thin-film optoelectronic devices. However, little is known about the dissolution pathway for metallic precursors in such mixtures. To exploit the full potential of this method, it is essential that a detailed understanding of the dissolution chemistry be developed. In this study, we use several characterization techniques to examine these solutions and then propose reaction mechanisms for In and Cu dissolutions in a hexylamine/1,2-ethanedithiol mixture. These dissolutions are rather found to be reactions resulting in metal oxidation with coevolution of H2 forming bis(1,2-ethanedithiolate)indium(III) in the case of indium dissolution and high nuclearity Cu(I) thiolate compounds in case of copper dissolution. This understanding allowed us to address the issue of toxicity and corrosivity associated with amine–thiol solvent by utilizing it as a reactant rather than a solvent for ink formulation. Here, we demonstrate a new approach whereby metal complexes formed by dissolving a range of metals including Cu, In, Zn, Sn, Se, and Ga with Se in amine–thiol solution can first be isolated by evaporation of the precursor solution and then dissolved in a variety of weakly coordinating organic solvents to provide a benign and stable solution free of unreacted amine and thiol for thin-film fabrication of various chalcogenide semiconductors. We utilize this new approach to demonstrate the fabrication of CuIn(S,Se)2 solar cells using dimethyl sulfoxide as a fabrication solvent.
Traditional fibre-optic drawing involves a thermally mediated geometric scaling where both the fibre materials and their relative positions are identical to those found in the fibre preform. To date, all thermally drawn fibres are limited to the preform composition and geometry. Here, we fabricate a metre-long crystalline silicon-core, silica-cladded fibre from a preform that does not contain any elemental silicon. An aluminium rod is inserted into a macroscopic silica tube and then thermally drawn. The aluminium atoms initially in the core reduce the silica, to produce silicon atoms and aluminium oxide molecules. The silicon atoms diffuse into the core, forming a large phase-separated molten silicon domain that is drawn into the crystalline silicon core fibre. The ability to produce crystalline silicon core fibre out of inexpensive aluminium and silica could pave the way for a simple and scalable method of incorporating silicon-based electronics and photonics into fibres.
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We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features a scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables the precise design of the length and thickness of the ledge and allows the careful balancing of performance against short-channel effects. We demonstrate L g =70 nm InAs MOSFETs with a ledge length of 5 nm that feature a record g m of 2.7 mS/μm. Separately, devices with a ledge length of 70 nm yield a record ON-current of 410 μA/μm (V dd =0.5 V and I off =100 nA/μm). We also demonstrate working MOSFETs with L g = 20 nm and a very tight metal contact spacing. Devices with a 5 nm ledge length reveal for the first time the existence of off-state leakage (GIDL) in III-V MOSFETs.Introduction InAs and InGaAs are promising channel material candidates for CMOS applications [1-6]. While great progress has taken place recently in demonstrating III-V MOSFETs, transistors displaying well-balanced electron transport, electrostatic integrity and parasitic resistance together with potential for high device density and tight pitch have yet to be demonstrated. We present here a wet-etch free process (no wet etching except for native oxide removal) for self-aligned InAs QW-MOSFETs that provides unprecedented control over the lateral dimensions of the gate access regions. We demonstrate devices with the highest transconductance and the highest ON-current of any III-V MOSFET to date.Fabrication Process Our new architecture leverages the self-aligned process presented in [2] but it incorporates new elements designed to implement highly conducting and tightly controlled channel access regions. In essence (Fig. 1), this is a gate-last process with the contacts formed first and the intrinsic region created by etching of the contact and cap layers. The gate is then nested in this opening in a self-aligned manner. In our new process, we use W above the Mo contact in order to prevent the oxidation of Mo during CVD SiO 2 deposition that in the past caused a deep lateral undercut during Mo RIE [2].The heart of our new process is a novel wet-etch free gate recess approach that provides unprecedented control over the vertical and lateral dimensions of the recess. This takes place in 3 steps (Fig. 2). The first step is time-controlled RIE of W/Mo sidewall [7] (Fig. 2a). Then the n + cap is removed by a low power Cl 2 -based anisotropic RIE (Fig. 2b), instead of the common peroxide based wet etch that results in an isotropic undercut [2-4]. It is observed that surface roughness strongly depends on RIE temperature. High temperature facilitates the removal of the etch byproducts from the surface, thus yielding a smooth surface. We used 130 o C with an etch rate of ~11 nm/min. The final step is a digital etch that separates the etch chemistry into its two components: surface oxidation (in O 2 plasma) and oxide removal (in H 2 SO 4 ), both of which are self-saturating (Fig.2c). It allows us to remove material in a contro...
Abstract-We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of lowpower O 2 plasma oxidation, followed by diluted H 2 SO 4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ∼0.9 nm/cycle. We illustrate the new process by fabricating L g = 60-nm selfaligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO 2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/µm (V ds = 0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V ds = 0.05 and 0.5 V, respectively, and ON current of 326 µA/µm at I OFF = 100 nA/µm and V dd = 0.5 V.
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