A new self-aligned quantum-well MOSFET architecture fabricated by a scalable tight-pitch process

Abstract

We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features a scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables the precise design of the length and thickness of the ledge and allows the careful balancing of performance against short-channel effects. We demonstrate L g =70 nm InAs MOSFETs with a ledge length of 5 nm that feature a record g m of 2.7 mS/μm. Separately, devices with a ledge length of 70 nm yield a record ON-current of 410 μA/μm (V dd =0.5 V and I off =100 nA/μm). We also demonstrate working MOSFETs with L g = 20 nm and a very tight metal contact spacing. Devices with a 5 nm ledge length reveal for the first time the existence of off-state leakage (GIDL) in III-V MOSFETs.Introduction InAs and InGaAs are promising channel material candidates for CMOS applications [1-6]. While great progress has taken place recently in demonstrating III-V MOSFETs, transistors displaying well-balanced electron transport, electrostatic integrity and parasitic resistance together with potential for high device density and tight pitch have yet to be demonstrated. We present here a wet-etch free process (no wet etching except for native oxide removal) for self-aligned InAs QW-MOSFETs that provides unprecedented control over the lateral dimensions of the gate access regions. We demonstrate devices with the highest transconductance and the highest ON-current of any III-V MOSFET to date.Fabrication Process Our new architecture leverages the self-aligned process presented in [2] but it incorporates new elements designed to implement highly conducting and tightly controlled channel access regions. In essence (Fig. 1), this is a gate-last process with the contacts formed first and the intrinsic region created by etching of the contact and cap layers. The gate is then nested in this opening in a self-aligned manner. In our new process, we use W above the Mo contact in order to prevent the oxidation of Mo during CVD SiO 2 deposition that in the past caused a deep lateral undercut during Mo RIE [2].The heart of our new process is a novel wet-etch free gate recess approach that provides unprecedented control over the vertical and lateral dimensions of the recess. This takes place in 3 steps (Fig. 2). The first step is time-controlled RIE of W/Mo sidewall [7] (Fig. 2a). Then the n + cap is removed by a low power Cl 2 -based anisotropic RIE (Fig. 2b), instead of the common peroxide based wet etch that results in an isotropic undercut [2-4]. It is observed that surface roughness strongly depends on RIE temperature. High temperature facilitates the removal of the etch byproducts from the surface, thus yielding a smooth surface. We used 130 o C with an etch rate of ~11 nm/min. The final step is a digital etch that separates the etch chemistry into its two components: surface oxidation (in O 2 plasma) and oxide removal (in H 2 SO 4 ), both of which are self-saturating (Fig.2c). It allows us to remove material in a contro...

III–V compound semiconductor transistors—from planar to nanowire structures

“…25 , 91 -94 For reference, the graph also shows InGaAs HEMTs, 95 which currently still set the highest mark for performance. Among InGaAs MOSFETs, planar designs reach the highest performance, 25 thanks to aggressive scaling and their self-aligned designs with low parasitics. However, as seen in Figure 3c , their I on drops signifi cantly for short gate lengths, indicating that the scaling potential of this architecture is limited.…”

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

“…At I off = 100 nA/μm and V dd = 0.5 V, it delivers an ON current of 326 μA/μm. This is the second highest value demonstrated in any III-V MOSFETs for L g ≤ 60 nm [2]- [6], [11]- [13]. A higher value has been recently demonstrated by using a combination of cap RIE etch and the digital etch presented here.…”

“…Usually the cap in a recessed-gate III-V FET heterostructure includes multiple layers of various semiconductors, such as InP and InAlAs [6], [13]. When those layers need to be recessed, even if the etch rate for those materials might be different, the method depicted in Fig.…”

“…First [ Fig. 1(a)], the top InGaAs cap is removed by well-established selective wet etching, leaving a gate recess opening (for tight lateral control, dry etching can also be used [13]). See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.…”

“…Digital etch techniques have been proposed to etch Silicon and III-Vs [7]- [13]. In this approach, the two elemental components of etching, oxidation and oxide removal, are applied separately.…”