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We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features a scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables the precise design of the length and thickness of the ledge and allows the careful balancing of performance against short-channel effects. We demonstrate L g =70 nm InAs MOSFETs with a ledge length of 5 nm that feature a record g m of 2.7 mS/μm. Separately, devices with a ledge length of 70 nm yield a record ON-current of 410 μA/μm (V dd =0.5 V and I off =100 nA/μm). We also demonstrate working MOSFETs with L g = 20 nm and a very tight metal contact spacing. Devices with a 5 nm ledge length reveal for the first time the existence of off-state leakage (GIDL) in III-V MOSFETs.Introduction InAs and InGaAs are promising channel material candidates for CMOS applications [1-6]. While great progress has taken place recently in demonstrating III-V MOSFETs, transistors displaying well-balanced electron transport, electrostatic integrity and parasitic resistance together with potential for high device density and tight pitch have yet to be demonstrated. We present here a wet-etch free process (no wet etching except for native oxide removal) for self-aligned InAs QW-MOSFETs that provides unprecedented control over the lateral dimensions of the gate access regions. We demonstrate devices with the highest transconductance and the highest ON-current of any III-V MOSFET to date.Fabrication Process Our new architecture leverages the self-aligned process presented in [2] but it incorporates new elements designed to implement highly conducting and tightly controlled channel access regions. In essence (Fig. 1), this is a gate-last process with the contacts formed first and the intrinsic region created by etching of the contact and cap layers. The gate is then nested in this opening in a self-aligned manner. In our new process, we use W above the Mo contact in order to prevent the oxidation of Mo during CVD SiO 2 deposition that in the past caused a deep lateral undercut during Mo RIE [2].The heart of our new process is a novel wet-etch free gate recess approach that provides unprecedented control over the vertical and lateral dimensions of the recess. This takes place in 3 steps (Fig. 2). The first step is time-controlled RIE of W/Mo sidewall [7] (Fig. 2a). Then the n + cap is removed by a low power Cl 2 -based anisotropic RIE (Fig. 2b), instead of the common peroxide based wet etch that results in an isotropic undercut [2-4]. It is observed that surface roughness strongly depends on RIE temperature. High temperature facilitates the removal of the etch byproducts from the surface, thus yielding a smooth surface. We used 130 o C with an etch rate of ~11 nm/min. The final step is a digital etch that separates the etch chemistry into its two components: surface oxidation (in O 2 plasma) and oxide removal (in H 2 SO 4 ), both of which are self-saturating (Fig.2c). It allows us to remove material in a contro...

Sub-30 nm III-V planar Quantum-Well (QW) n-type MOSFETs are fabricated through a self-aligned CMOS compatible front-end process. Good performance and short-channel effect mitigation are obtained through the use of a QW-channel that incorporates a thin pure InAs subchannel and extremely scaled HfO 2 gate dielectric on a very thin InP barrier (total barrier EOT<1 nm). The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. At L g =30 nm, transconductance of 1420 μS/μm and subthreshold swing of 114 mV/dec at 0.5 V are obtained. However, a III-V MOSFET structure that combines high performance, ability to harmoniously scale down to sub-30 nm gate length dimensions and CMOS-type manufacturability is still to be realized. In this work, we demonstrate a novel QW-MOSFET that addresses these challenges. For this, we use an extremely-scaled HfO 2 gate insulator. The fabrication closely follows CMOS requirements, particularly self-alignment of the refractory metal gate and metal contacts, very low thermal budget, gate-last process that uses RIE extensively and an entirely lift-off free process in the frontend. MOSFETs with gate length dimensions in the 20-30 nm range and outstanding electrical characteristics are obtained.

Abstract-We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of lowpower O 2 plasma oxidation, followed by diluted H 2 SO 4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ∼0.9 nm/cycle. We illustrate the new process by fabricating L g = 60-nm selfaligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO 2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/µm (V ds = 0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V ds = 0.05 and 0.5 V, respectively, and ON current of 326 µA/µm at I OFF = 100 nA/µm and V dd = 0.5 V.

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