Nanometer-Scale III-V MOSFETs

Sub-10-nm-Diameter InGaAs Vertical Nanowire MOSFETs: Ni Versus Mo Contacts

“…6 is the ideal relationship obtained from electrostatic simulations [28]. Multiple reports from the literature, including some of our own [21], show S lin substantially worse than the ideal value. This is attributed to poor gate efficiency due to oxide/semiconductor interface traps [27].…”

“…A critical challenge to obtain functional sub-10 nm VNW devices is contacting the tiny NW top. The use of Mo, which yields state-of-the-art contact resistance in planar transistors [21], becomes ineffective as top contact in narrow fins and NWs because of the existence of a "deadzone" under the metal [21]. Even in the case of a Mo contact to a heavily-doped InGaAs region, the outermost ~10 nm sub-surface layer beneath the sidewall ends up being non-conducting.…”

1/f and RTS noise in InGaAs nanowire MOSFETs

“…Utilizing nanowires (NWs) as the channel in such devices offers improved electrostatic control and enables the use of highly scaled gate lengths [1]. However, due to the lack of a native oxide, the trap density in III-V FETs is typically high (compared with Si/SiO2 devices), which can degrade the transistor performance and reliability significantly [2].…”

Tb/Ni/TiN Stack for Ultralow Contact Resistive Ni‐Tb‐InGaAs Alloy to n‐In0.53Ga0.47As Layer

“…Ni‐InGaAs has a low and uniform sheet resistance, low Schottky barrier height of approximately 0.1 eV (pinning near conduction band), and good crystalline orientation with substrates . However, to the best of our knowledge, the reported specific contact resistivity ( ρ c ) between Ni‐InGaAs and the doped S/D is approximately 10 −6 Ω cm 2 , which is far from the requirement of scaled devices . Moreover, continuous scaling may worsen this issue, in the future.…”

“…More study is needed to investigate the effects of Tb on the Ni‐InGaAs system. The optimization of the Ni‐Tb‐InGaAs system seems to be promising to satisfy the requirement of ρ c , which must be less than 1 × 10 −9 Ω cm 2 in future high performance InGaAs devices …”