This paper presents a global routing algorithm that minimizes total wire length and satisfies RLC crosstalk constraints specified at sinks. Our algorithm is based on critical network concept and search space traversing technology (SSTT) for global routing synthesis and Tabu search for shield insertion and net ordering (SINO) to eliminate noise. The algorithm achieves about 20x speedup compared with a recent work using iterative deletion based global routing and simulated annealing based SINO. Furthermore, our algorithm increases the wire length by 4% compared with global routing without crosstalk constraints, achieving a 2.5x reduction compared with the aforementioned recent work.
In this paper, we present power models with clock and temperature scaling, and develop the first of its type coupled thermal and power simulation with temperature-dependent leakage power model at micro-architecture level. We show that leakage energy and total energy can be different by up to 2.5X and 2X for temperatures between 90 o C and 130 o C, respectively. Given such big energy variations, no power model at microarchitecture level is accurate without considering temperature dependent leakage models.
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: the min-area sleep transistor insertion (and sizing) (T IS) problem with respect to a fixed P/G network, and the simultaneous sleep transistor insertion and P/G network sizing (T IP GS) problem to minimize the weighted area of sleep transistors and P/G network. We show that there may exist multiple sleep transistor insertion solutions that all lead to a same minimum area in the T IS and T IP GS problems. We develop optimal algorithms to T IS and T IP GS problems by modeling the circuit as a single current source, and then extend to the case modeling the circuit as distributed current sources. Compared with the best known approach, our algorithms achieve area reduction by up to 44.1% and 61.3% for T IS and T IP GS, respectively.
Abstract. Power is rapidly becoming the primary design constraint for systems ranging from server computers to handhelds. In this paper we study microarchitecture-level coupled power and thermal simulation considering dynamic and leakage power models with temperature and voltage scaling. We develop an accurate temperature-dependent leakage power model and efficient temperature calculation, and show that leakage energy can be different by up to 10X for temperatures between 35 o C and 110 o C. Given the growing significance of leakage power and its sensitive dependence on temperature, no power simulation without considering dynamic temperature calculation is accurate. Furthermore, we discuss the thermal runaway induced by the interdependence between leakage power and temperature, and show that in the near future thermal runaway could be a severe problem. We also study the microarchitecture level coupled power and thermal management by novel active cooling techniques that reduce packaging thermal resistance. We show that the active cooling technique that reduces thermal resistance from 0.8 o C/W to 0.05 o C/W can increase system maximum clock by up to 2.44X under the same thermal constraints.
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