Proceedings of the 41st Annual Design Automation Conference 2004
DOI: 10.1145/996566.996742
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Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects

Abstract: Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: the min-area sleep transistor insertion (and sizing) (T IS) problem with respect to a fixed P/G network, and the simultaneous sleep transistor insertion and P/G network sizing (T IP GS) problem to minimize the weighted area of sleep transistors and P/G network. We show that there may exist multiple sleep transistor insertion solutions … Show more

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Cited by 33 publications
(24 citation statements)
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“…We believe an abstract model can be developed readily starting from this. Alternatively, we may seek techniques for developing an abstract model from a cycle-true simulation, possibly similar in nature to the techniques proposed in [LSLH04]. It remains to be seen how accurate such an approach would be, however.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…We believe an abstract model can be developed readily starting from this. Alternatively, we may seek techniques for developing an abstract model from a cycle-true simulation, possibly similar in nature to the techniques proposed in [LSLH04]. It remains to be seen how accurate such an approach would be, however.…”
Section: Discussionmentioning
confidence: 99%
“…This model is used to guide the floorplanning process. While [LSLH04] cites reasonably good fidelity of the model in their experiments, it is not clear how well this approach will scale. With the increasing impact of interconnect delay, floorplanning will have a greater effect on the delays, and thus there is an increasing need to evaluate the system performance model at points further away from the initial characterization.…”
Section: Existing Workmentioning
confidence: 99%
“…Furthermore, the DOE method also provides a framework for estimating the interactions between the inputs. While [LSLH04] consists of simultaneously changing the bus latencies, it does not model any interactions between buses. As will be seen later in Sec- …”
Section: Related Workmentioning
confidence: 99%
“…This method proposes a suitable strategy for treatment of nonlinearities which presents the real bottleneck of model order reduction. This method has been applied on several nonlinear problems especially to electronics engineering applications [12][13][14][15][16][17][18][19]. A similar method to the one adopted in this paper is found in the work of Bugard et al [20] and Panzer et al [21] who have proposed a parametric model order reduction.…”
Section: Introductionmentioning
confidence: 95%