System level leakage reduction considering the interdependence of temperature and leakage

He, Lei; Liao, Weiping; Stan, Mircea R.

doi:10.1145/996566.996572

Cited by 71 publications

(45 citation statements)

References 22 publications

(29 reference statements)

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“…With the proposed design flow, potential thermal hazards such as leakageinduced thermal runaway should be discovered as early in the design process as possible. With the help of a compact chip and package level thermal model, across-die temperature distribution can be estimated at design time, which permits thermally selfconsistent leakage power calculations in an iterative manner as shown in [21], [22]. This is illustrated by an example of potential thermal runaway for a SoC design.…”

Section: Related Workmentioning

confidence: 99%

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

Huang

Sankaranarayanan

Skadron

et al. 2008

IEEE Trans. Comput.

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Abstract-Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To achieve this, an accurate yet fast temperature model together with an early-stage, thermally optimized, design flow are needed. In this paper, we present an improved block-based compact thermal model (HotSpot 4.0) that automatically achieves good accuracy even under extreme conditions. The model has been extensively validated with detailed finite-element thermal simulation tools. We also show that properly modeling package components and applying the right boundary conditions are crucial to making full-chip thermal models like HotSpot accurately resemble what happens in the real world. Ignoring or oversimplifying package components can lead to inaccurate temperature estimations and potential thermal hazards that are costly to fix in later designs stages. Such a full-chip and package thermal model can then be incorporated into a thermally optimized design flow where it acts as an efficient communication medium among computer architects, circuit designers and package designers in early microprocessor design stages, to achieve early and accurate design decisions and also faster design convergence. For example, the temperature-leakage interaction can be readily analyzed within such a design flow to predict potential thermal hazards such as thermal runaway. An example SoC design illustrates the importance of adopting such a thermally optimized design flow in early design stages.Index Terms-compact thermal model, early design stages, leakage, parameterized model, temperature, thermally optimized design flow.

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Section: Related Workmentioning

confidence: 99%

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

Huang

Sankaranarayanan

Skadron

et al. 2008

IEEE Trans. Comput.

Self Cite

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“…Having a uniform temperature distribution has several advantages: lowers the probability of failure [10], contributes against the exponential increase of both static and dynamic power dissipation [11] and can lead to higher performance as well [12]. Several solutions have been proposed, but none of them was able to consider the floorplanning problem at a high level of abstraction: most of the works like [13] take in consideration sub-circuit partitioning or routing tracks [14]; others [15], [16] are more focused on power models.…”

Section: Introductionmentioning

confidence: 99%

Thermal-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems

Pagano

Vuka

Rabozzi

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Field Programmable Gate Arrays (FPGAs) systems are being more and more frequent in high performance applications. Temperature affects both reliability and performance, therefore its optimization has become challenging for system designers. In this work we present a novel thermal aware floorplanner based on both Simulated Annealing (SA) and MixedInteger Linear Programming (MILP). The proposed method takes into account an accurate description of heterogeneous resources and partially reconfigurable constraints of recent FPGAs. Our major contribution is to provide a high level formulation for the problem, without resorting to low level consideration about FPGAs resources. Within our approach we combine the benefits of SA and MILP to handle both linear and non-linear optimization metrics while providing an effective exploration of the solution space. Experimental results show that, for several designs, it is possible to reduce the peak temperature by taking into account power consumption during the floorplanning stage.

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“…Unfortunately, leakage power consumption is particularly severe in this case, due to the high die temperature when circuits are active. The positive loop between active mode leakage consumption and high die temperature can even cause a phenomenon called "thermal runaway" and lead to catastrophic thermal failure [2]. Thus, more aggressive leakage control is desirable, especially for active circuits with only short idleness.…”

Section: Introductionmentioning

confidence: 99%