Leakage power modeling and reduction with data retention

Liao, Weiping; Basile, Joseph M.; He, Lei

doi:10.1145/774572.774677

Cited by 38 publications

(42 citation statements)

References 8 publications

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“…Current microarchitecture-level power simulators [5,6,7] calculate leakage power by assuming a ratio between dynamic and leakage power. For example, [7] determines the ratio for logic circuits by SPICE simulations on typical circuits and also presents formula-based models for leakage power in memory based units.…”

Section: Prior Related Workmentioning

confidence: 99%

“…For example, [7] determines the ratio for logic circuits by SPICE simulations on typical circuits and also presents formula-based models for leakage power in memory based units. Such models [5,6,7] are efficient for microarchitectural simulations because dynamic power calculations within the model can therefore automatically compute the contribution of leakage power. However, as discussed previously, this assumption is not accurate as dynamic power and leakage power scale differently as a function of supply voltage and temperature.…”

Section: Prior Related Workmentioning

confidence: 99%

“…(iii) inactive mode, where a circuit is deactivated by power gating [12] or other leakage reduction techniques, and dissipates a reduced leakage power defined as inactive power (Pi). A circuit in the inactive mode requires a non-negligible amount of time to wake up and then perform an useful operation [7]. In cycle accurate simulations, power is defined as the energy per clock cycle.…”

Section: Power Model With Temperature and Voltage Scalingmentioning

confidence: 99%

“…We integrate our thermal and power model into the PowerImpact [7] toolset. The microarchitecture components in our VLIW processor include BTB, L1 instruction cache, L1 data cache, unified L2 cache, integer register file, floating-point register file, decoder units, integer units (IALUs) and floating-point units (FPUs).…”

Section: Experiments Parameter Settingsmentioning

confidence: 99%

“…Figure 2 clearly shows that any study regarding leakage energy is not accurate if the thermal issue is not considered. To consider temperature in methods in [7,18], the designers need to assume a fixed temperature appropriate for the processor and the environment, and then use leakage values at this temperature. How to decide the appropriate temperature is of paramount importance for accurate energy estimation, and it is an open problem in the literature.…”

Section: Chip Temperaturementioning

confidence: 99%

See 4 more Smart Citations

Modeling of coplanar waveguide for buffered clock tree

Chen¹,

He²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Power is rapidly becoming the primary design constrain for systems ranging from server computers to handhelds. In this paper we study microarchitecture-level power modeling and management with temperature and voltage scaling. We develop an accurate temperature-dependent leakage power model and efficient temperature calculation, and show that leakage energy and total energy can be different by up to 10X and 30% for temperatures between 35 o C and 110 o C, respectively. Given the growing significance of leakage power and its sensitive dependence on temperature, no power modeling at microarchitecture is accurate without considering dynamic temperature calculation. Furthermore, we discuss a new thermal runaway phenomenon induced by the temperature dependent leakage power and show that in the near future thermal runaway could be a severe problem. We also study the microarchitecture level coupled power and thermal management by clock gating and novel active cooling techniques. We show that with thermal constraints, clock gating can increase maximum system clock by up to 1.5X and reduce leakage energy by up to 68.5% compared to the cases without clock gating, and active cooling techniques providing smaller thermal resistance can further increase the maximum clock by a factor of 2.44X.

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Section: Prior Related Workmentioning

confidence: 99%

Section: Prior Related Workmentioning

confidence: 99%

Section: Power Model With Temperature and Voltage Scalingmentioning

confidence: 99%

Section: Experiments Parameter Settingsmentioning

confidence: 99%

Section: Chip Temperaturementioning

confidence: 99%

See 3 more Smart Citations

Modeling of coplanar waveguide for buffered clock tree

Chen¹,

He²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA

Gebotys

Tiu

2005

Cryptographic Hardware and Embedded Systems – CHES 2005

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Abstract. Although many wireless portable devices offer more resistance to bus probing and power analysis due to their compact size, susceptibility to electromagnetic (EM) attacks must be analyzed. This paper demonstrates, for the first time, a real EM-based attack on a PDA running Rijndael and elliptic curve cryptography. A new frequency-based differential EM analysis, which computes the spectrogram, is presented. Additionally a low energy countermeasure for symmetric key cryptography is presented which avoids large overheads of table regeneration or excessive storage. Unlike previous research the new differential analysis does not require perfect alignment of EM traces, thus supporting attacks on real embedded systems. This research is important for future wireless embedded systems which will increasingly demand higher levels of security.

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Power Consumption Analysis of Embedded Multimedia Application

Chen

Dong

et al. 2005

Embedded Software and Systems

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Leakage power modeling and reduction with data retention

Cited by 38 publications

References 8 publications

Modeling of coplanar waveguide for buffered clock tree

Modeling of coplanar waveguide for buffered clock tree

EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA

Power Consumption Analysis of Embedded Multimedia Application

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