Modeling of coplanar waveguide for buffered clock tree

Abstract

Power is rapidly becoming the primary design constrain for systems ranging from server computers to handhelds. In this paper we study microarchitecture-level power modeling and management with temperature and voltage scaling. We develop an accurate temperature-dependent leakage power model and efficient temperature calculation, and show that leakage energy and total energy can be different by up to 10X and 30% for temperatures between 35 o C and 110 o C, respectively. Given the growing significance of leakage power and its sensitive dependence on temperature, no power modeling at microarchitecture is accurate without considering dynamic temperature calculation. Furthermore, we discuss a new thermal runaway phenomenon induced by the temperature dependent leakage power and show that in the near future thermal runaway could be a severe problem. We also study the microarchitecture level coupled power and thermal management by clock gating and novel active cooling techniques. We show that with thermal constraints, clock gating can increase maximum system clock by up to 1.5X and reduce leakage energy by up to 68.5% compared to the cases without clock gating, and active cooling techniques providing smaller thermal resistance can further increase the maximum clock by a factor of 2.44X.

High-level area and power-up current estimation considering rich cell library

“…It includes three steps: 1. transform the system to a new system without loading capacitance; 2. construct wave-form for step input; 3. construct waveform for ramp input. We will briefly explain these steps in this section, more detailed derivation can be found in a technical report [7].…”