Abstract-Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. In this paper, we first propose a piece-wise linear (PWL) model for the far-end response of a CPW considering ramp input and capacitive loading. The PWL model has a high accuracy but uses at least 1000x less time compared to SPICE. We then apply the PWL model to synthesize the CPW geometry for clock trees considering constrains of rising time and oscillation at sinks. We obtain a spectrum of solutions with smooth tradeoff between area and power.
In this paper, we study leakage power reduction using power gating in the farms of the Virtual power/ground Rails Clamp (VRC) and Multi-threshold CMOS (MTCMOS) techniques.We apply power gating to two circuit types: memory-based units and datapath components. Using a microarchitecturelevel power simulator, as well as power and timing models derived from detailed circuit d e s i p , we further study leakage power modeling and reduction at the system level for modem high-performance VLlW processors. We show that the leakage power can be over 40% of the total power for such processors. Moreover, we propose time-out scheduling of VRC to reduce power up to 85.65% for L2 cache. This power savings results in close to 113 total power dissipation for the VLlW processors we study. 0-7803-7607-2/02/517.00 Q 2002 IEEE
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