Leakage power modeling and reduction with data retention

Abstract

In this paper, we study leakage power reduction using power gating in the farms of the Virtual power/ground Rails Clamp (VRC) and Multi-threshold CMOS (MTCMOS) techniques.We apply power gating to two circuit types: memory-based units and datapath components. Using a microarchitecturelevel power simulator, as well as power and timing models derived from detailed circuit d e s i p , we further study leakage power modeling and reduction at the system level for modem high-performance VLlW processors. We show that the leakage power can be over 40% of the total power for such processors. Moreover, we propose time-out scheduling of VRC to reduce power up to 85.65% for L2 cache. This power savings results in close to 113 total power dissipation for the VLlW processors we study. 0-7803-7607-2/02/517.00 Q 2002 IEEE