Microarchitecture level power and thermal simulation considering temperature dependent leakage model

Abstract

In this paper, we present power models with clock and temperature scaling, and develop the first of its type coupled thermal and power simulation with temperature-dependent leakage power model at micro-architecture level. We show that leakage energy and total energy can be different by up to 2.5X and 2X for temperatures between 90 o C and 130 o C, respectively. Given such big energy variations, no power model at microarchitecture level is accurate without considering temperature dependent leakage models.

Modeling of coplanar waveguide for buffered clock tree

“…More importantly, [8] does not consider temperature scaling and the exponential supply voltage dependence of I leakage . [9] proposes a leakage power model with temperature scaling for 100nm technology. Different formulas for logic circuits and memory circuits are proposed in [9].…”

“…[9] proposes a leakage power model with temperature scaling for 100nm technology. Different formulas for logic circuits and memory circuits are proposed in [9]. For logic circuits, the leakage power is calculated as the product of gate count (Ngate) and the average leakage current per gate (Iavg), as shown in (2):…”

“…[9] provides temperature dependent formulas for both Iavg for logic circuits 1 and Pso for SRAM arrays. However, the temperature dependence is characterized by a purely empirical exponential term exp( −a T −b ) without providing a theoretical model where a and b are coefficients and T is the temperature which can be extended to future technology generations.…”

“…However, the temperature dependence is characterized by a purely empirical exponential term exp( −a T −b ) without providing a theoretical model where a and b are coefficients and T is the temperature which can be extended to future technology generations. Voltage scaling is not consider for either dynamic or leakage power in [9]. [9] considers thermal calculation based on the whole chip and individual modules, but the thermal resistance for all modules only have relative value and refer to the thermal resistance of one integer unit decided by an empirical assumption.…”

“…Voltage scaling is not consider for either dynamic or leakage power in [9]. [9] considers thermal calculation based on the whole chip and individual modules, but the thermal resistance for all modules only have relative value and refer to the thermal resistance of one integer unit decided by an empirical assumption. [9] studies the on-chip temperature up to 130 o C, which is too high for current packaging techniques to support.…”