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This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at V DS =0.5V.

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In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin T OXE of 20.5Å with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for low power logic applications. IntroductionNon-planar, multi-gate architectures have been investigated for improved electrostatics in Si MOSFETs [1], and most recently in III-V MOSFETs [2]. In this work, nonplanar, multi-gate InGaAs QWFETs with high-K gate dielectric and ultra-scaled L SIDE of 5nm are reported. These non-planar, multi-gate QWFET devices have undoped InGaAs channel in the shape of a "fin" formed on top of large band gap InAlAs barrier, with simplified n ++ InGaAs source/drain scheme. Compared to the planar high-K InGaAs QWFET with similar electrical oxide thickness (T OXE ), the non-planar, multi-gate QWFET devices in this work show (i) more enhancement-mode threshold voltage (V T ) and (ii) significantly improved electrostatics with reducing transistor gate length (L G ) due to stronger gate control of the channel. In addition, the ultra-scaled L SIDE combined with the simplified n ++ InGaAs source/drain (S/D) scheme will enable device footprint scaling.