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Summary In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Qinv) at the ‘virtual‐cathode’ reaches to a critical charge Qth. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.

Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.

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