In this paper, self-tuned, rule-optimized multiinput and multi-output (MIMO) fuzzy logic controller (FLC) is implemented on field programmable gate arrays (FPGA). The design of membership functions, rule base are made with aid of genetic algorithm (GA). Flexibility in FPGA design is implemented through tuning of FLC parameters. The system is modularized as rule base development, rule base transfer and computations on FPGA. Based on the system, an experimental dataset is obtained, which is utilized in a capable computing platform so as to develop a fine-tuned fuzzy rule base. The synthesized rule base is transferred to FPGA along with user provided inputs through a GUI. The GUI also displays the output result sent by FPGA. The communication between the GUI and the FPGA is done via universal asynchronous receiver and transmitter. Rule-optimized FLC is implemented on Xilinx Virtex-5 LX110T board. This dedicated single chip architecture performs high-speed fuzzy inferences with processing speed up to 760 KFLIPS at a clock frequency of 247 MHz using 8 rules, 2 input variables at 16-bit resolution. Experiments of software implementation and hard-
Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.
In this paper, an efficient automatic diagnosis system for pneumonia classification is developed using extracted textural features obtained from appropriate wavelet transformation. For feature extraction and analysis in the classification of pneumonia, different wavelet families such as Db3.3, Rbio3.3, Rbio3.5, and Rbio 3.7 are explored. The optimum feature extraction for distinguishing pneumonia infected lungs from normal lungs comes from combining the Db3.3 and Rbio3.7 wavelet families. The features extracted from Db3.3 and Rbio3.7 wavelets are analyzed by feeding to different supervised learning classifiers. It is observed that SVM with RBF kernel is attaining maximum accuracy of 97.5% with σ=2 in the classification. The RBF kernel, on the other hand, is hampered by its lengthy testing computation time. This paper introduces a novel backward elimination based SVM (BESVM) in order to reduce computation time. The suggested method's experimental findings demonstrate the trade‐off between classification speed and performance. This was also noticed when targeting a real‐time hardware software codesign FPGA environment. The amount of support vectors is optimized using the BESVM technique, resulting in a 30% reduction in resource utilization and a 590 ns delay while maintaining accuracy. In terms of area, latency, and hardware efficiency, the suggested BESVM‐based hardware design demonstrates its efficacy.
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