Hardware‐efficient approximate logarithmic division with improved accuracy

Abstract

Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.

Logarithmic division for green feature selection: an information-theoretic approach

“…For further study, we opted for a more realistic implementation based on the one provided by Meurant [8] for the Matlab tool, but some modifications have been introduced, including the addition of logarithmic division. Regarding the division, Mitchell's algorithm has been chosen, since it is known for its efficiency in terms of energy consumption, silicon area and time [9]. This, together with the simple implementation of this algorithm using fixed-point representation, makes it a promising option for obtaining even more energy-efficient feature selection methods.…”

Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing

“…SC belongs to approximate computing paradigm which can reduce the hardware cost of the circuit. 5,6 Converting real numbers into SNs requires stochastic number generators (SNGs). Generally, an SNG consists of two components, a random number generator (RNG) and a comparator (CMP).…”

“…For example, a real number x is represented by an SN X , where x = P( X ), meaning the probability of 1 s in X , and 0 ≤ x ≤ 1. SC belongs to approximate computing paradigm which can reduce the hardware cost of the circuit 5,6 . Converting real numbers into SNs requires stochastic number generators (SNGs).…”