Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

Tiwari, Pramod Kumar; Samoju, Visweswara Rao; Sunkara, Thandva; Dubey, Sarvesh; Jit, Satyabrata

doi:10.1007/s10825-016-0819-0

Cited by 26 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It determines V TH at a critical user-defined value of the drain current (I Dcc ). In this paper we use one initially proposed by Tsuno et al [28] for MOSFETs and later adapted for NWs by Tiwari et al [29] where the constant drain current is set to 100nAx(W m /L m ). L m and W m refer to the channel length and channel perimeter of the device, respectively.…”

Section: Device Description and Simulation Methodologymentioning

confidence: 99%

Does the Threshold Voltage Extraction Method Affect Device Variability?

Espineira

García‐Loureiro

Seoane

2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

Section: Device Description and Simulation Methodologymentioning

confidence: 99%

Does the Threshold Voltage Extraction Method Affect Device Variability?

Espineira

García‐Loureiro

Seoane

2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

“…JL-DGAA-NT FET can be explored with HD gate oxide engineering technique. Since, spacers are considered very crucial for the NT FETs [20][21][22][23], all simulation have been performed with different dielectric as spacer and investigated.…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

“…As side spacer is considered as foremost design parameter of NT FETs [20][21][22][23]. Therefore, performance of JL-DGAA-NT FET and HD-JL-DGAA-NT FET with different spacer dielectric constant has been analysed.…”

Section: Off Current and I On /I Off Ratio Variation With Respect To Different Spacer Dielectric Constantmentioning

confidence: 99%

“…Recently, double gate all around Nanotube (DGAA-NT) transistor with inner (core gate) and outer gates was proposed to have efficient gate control over the channel, leading to provide better SCEs immunity compared to NW FETs [17][18][19][20][21][22][23]. Silicon and heterostructure nanotube based tunnel FETs nanotube-based were also proposed and investigated [24,25].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Kumar

2020

Silicon

View full text Add to dashboard Cite

This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO 2 and Hf x Ti 1-x O 2 ) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO 2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10 −14 to 10 −17 and I ON /I OFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and I ON /I OFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

show abstract

“…By using the constant current method (CC method), the value of the threshold voltage can be taken out. By using this method the V th can be measured corresponding to a constant current, on this constant current the value if V GS is known as the threshold voltage (V th ) [21].…”

Section: Device Structurementioning

confidence: 99%

Design and performance analysis of A Triple Material Double Gate Cylindrical Gate All Around (TMDG CGAA) MOSFET in Nano-meter Regime

Menaria¹,

Pandey²

2020

SKIT Research Journal

View full text Add to dashboard Cite

The current work deals with the designing and performance analysis of a Triple Material Double Gate Cylindrical Gate All Around (TMDG-CGAA) MOSFET in the nanometer regime. The proposed structure has combined the gate engineering technique by used a double gate structure and the material engineering techniques by used three different materials in the gate electrode to incorporate the benefits of both the techniques. The proposed structure has been verified by using the ATLAS tool, which is a 3-dimensional tool. A comparative study of SG-CGAA, DG-CGAA, DMDG-CGAA, and TMDG-CGAA has been accomplished by using the same device parameters. The threshold voltage (Vth) is extracted from the transfer characteristic of the above MOSFETs. Along with the threshold voltage extraction the other parameters like DIBL and I on /I off ratio are also calculated. Results disclosed that the TMDG-CGAA MOSFET gives better immunity to the SCEs like DIBL. Also, the ratio of on current is to off current is also high in the TMDG-CGAA MOSFET in comparison to SG CGAA MOSFET and DGDM-CGAA MOSFET structures. In the short channel planar devices, the potential barrier is reducing so that the threshold voltage is also reducing. But in the proposed structure the device shows better performance, it increases gate controllability and reducing the SCEs and increment in the high drain current along with the high packaging density, which is needed in the application of Ultra Large Scale Integration (ULSI).

show abstract

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

Cited by 26 publications

References 11 publications

Does the Threshold Voltage Extraction Method Affect Device Variability?

Does the Threshold Voltage Extraction Method Affect Device Variability?

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Design and performance analysis of A Triple Material Double Gate Cylindrical Gate All Around (TMDG CGAA) MOSFET in Nano-meter Regime

Contact Info

Product

Resources

About