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We have studied the gaseous hydrochloric acid selective etching of SiGe versus silicon in a reduced pressure-chemical vapor deposition reactor. Non-classical metal oxide semiconductor field effect transistors (MOSFETs) architectures, such as silicon on nothing (SON) and multi-bridge channels (MBC) devices require high SiGe:Si etch selectivities in order to get rid of the sacrificial SiGe layers. We have probed the in situ HCl etching of Si and SiGe blanket layers of SiGe/Si stacks grown selectively in the Si windows of patterned wafers ('SON-like' substrates) and of SiGe/Si superlattices ('MBC-like' substrates) as a function of the reverse absolute temperature. A switch from high temperature, diffusion-limited/low temperature, Cl-desorption-limited etch regimes to a unique LT regime, together with a significant etch rate increase, has been evidenced when drastically increasing the HCl partial pressure. Very good selectivities (versus Si) have been obtained when laterally etching high Ge content Si 1−x Ge x layers (typically 30%). A preferential etch by HCl of the {1 0 0} crystallographic planes compared to the {1 1 0} ones has been noticed both for the lateral etch of the 'SON-like' patterns (preferential etch of the pattern corners) and for the 'MBC-like' patterns (fullsheet (0 0 1) etch rates ≈10 times the {1 1 0} lateral etch rates). A slight etch rate difference between 'bottom-located' and 'top-located' Si 1−x Ge x layers in Si/SiGe superlattices has also been highlighted. This etching technique is thus usable for the processing of SON or MBC devices provided that the selective {1 0 0}:{1 1 0} HCl etch reported here is taken into account.

We have first investigated the influence of the in situ H 2 bake temperature (between 750 • C and 850 • C) on (1 0 0) and (1 1 0) fullsheet surface preparations (after 'HF-last' wet cleaning). A strong increase of the (1 1 0) surface roughness occurred when baking between 750 and 775 • C, with high C and O contamination peaks at the Si substrate/Si overlayer interface. A high H 2 bake temperature ( 800 • C) is thus mandatory for both (1 0 0) and (1 1 0) Si surfaces. We have also studied the 750 • C-950 • C, high HCl partial pressure etch of blanket Si wafers. HCl etch rates are roughly four times higher on (1 1 0) than on (1 0 0). Etch rate activation energies are however quite close to each other (57 kcal mol −1 on (1 0 0) ⇔ 59 kcal mol −1 on (1 0 0)), suggesting similar etch-limiting mechanisms. We have then investigated the low-temperature growth of high Ge content (10-37%) SiGe layers on blanket Si wafers with dichlorosilane + germane chemistry (selective versus SiO 2 on patterned wafers). The SiGe growth rate on (1 1 0) bows downwards from linearity and then saturates when increasing the germane mass flow. In contrast, it almost linearly increases on (1 0 0) surfaces, reaching values more than three times higher than on (1 1 0). A parabolic relationship between experimental Ge concentrations and the F(GeH 4 )/F(SiH 2 Cl 2 ) mass-flow ratio has been evidenced on (1 0 0). In contrast, a linear relationship links the (1 1 0) Ge concentration to the F(GeH 4 )/F(SiH 2 Cl 2 ) mass-flow ratio. Finally, 63 and 65 kcal mol −1 activation energies are associated with the fullsheet Si growth rate increase with the inverse absolute temperature on (1 0 0) and (1 1 0) (dichlorosilane chemistry). The GR (1 1 0) /GR (1 0 0) Si growth rate ratio, ≈0.74, is close to the dangling bond surface density (DBSD) ratio (DBSD (1 1 0) /DBSD (1 0 0) ≈ 0.71). Such growth rate discrepancies are thus justified by these DBSD differences. Results obtained on fullsheet wafers have been used to selectively grow SiGe/Si stacks on (1 0 0) and (1 1 0) patterned Si wafers for silicon-on-nothing and localized-silicon-on-insulator purposes, respectively.

We report on the characterization, thanks to Raman spectroscopy and imaging of tensely strained Si films pseudomorphically grown on (001), (110), and (111) SiGe virtual substrates. The samples studied here are those described in the work of Destefanis et al. [J. Appl. Phys 106, 043508 (2009)]. They consist in 17-nm-thick strained Si layers grown at 650 °C with SiH4 as a gaseous precursor on top of polished SiGe virtual substrates of various surface orientations. We first derived the exact component array of the strain/stress field along the different growth directions. Because the relation between strain or stress and the Raman frequencies are complex, we also derive the strain-shift coefficients for the different substrate orientations considered in this work and the polarization selection rules. Visible and near-UV Raman spectroscopies were used to extract the in-plane lattice parameter of the SiGe virtual substrates and the tensile strain in the thin Si epitaxial layers on top. We have notably investigated thanks to Raman imaging the in-plane distribution of strain in Si layer/SiGe buffer stacks grown on (110) and (111) Si substrates. Original surface arrays have been highlighted for each surface orientation. Promising results have been obtained for (110) SiGe virtual substrates in terms of strain and layer quality while the technological usefulness of the (111) ones is more questionable.

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We have studied the low temperature (~ 650oC), high HCl partial pressure (180 Torr) selective etch of SiGe versus Si inside a RP-CVD reactor. The surface roughness strongly increases while vertically etching fullsheet Si1-xGex layers. We have also laterally etched (Si / SiGe) multilayers patterned along the <110> directions. The best selectivities and the highest SiGe etch rates have been obtained for the highest Ge content studied, i.e. 40%. <111> facets have been revealed at the end of tunnels. A strong increase (x 18) of the <110> lateral HCl etch rates has been evidenced when increasing the Si0.6Ge0.4 layer thickness from 5 up to 20 nm. Very good SiGe versus Si selectivities have been obtained with slightly higher etch rates than on bulk Si when HCl etching (Si / SiGe) multilayers grown on Si0.8Ge0.2 virtual substrates. Finally, a strong HCl etch in-plane anisotropy has always been evidenced. <100> oriented pattern corners are indeed far more etched than <110> oriented edges.

The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 • C in windows of patterned wafers are rough, we have first of all studied the 600 • C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 • C down to 600 • C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 • C and 725 • C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 • C on (1 0 0) or at 600 • C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5-3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were notably obtained for the lateral etching of the (1 1 0) and (1 0 0) SiGe sacrificial layers (thanks to a CF 4 -based dry plasma), with no anisotropy. Significant hole mobility gains (electron mobility loss) compared to the universal Si(1 0 0)/SiO 2 mobility were evidenced in long, narrow (L = 10 μm; W = 0.08 μm) 'bulk-like' epitaxial Si(1 1 0) L-SOI devices (i.e. with SiGe still present under most of the Si channel). The gain (the loss) monotonically increased from 120% (11%) up to 246% (58%) when moving away from the [0 0 1] direction toward the [1 −1 0] direction (not reached, however: at most at 60 • to [0 0 1]). Vastly improved hole transport properties (a factor of 2 On current increase) were evidenced in short dimensions L-SOI devices (L = 0.35 μm; W = 0.08 μm) when switching from (1 0 0) surfaces with 1 1 0 conduction channels to (1 1 0) surfaces with a [0 0 1] propagation direction for the holes.

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