2008
DOI: 10.1016/j.jcrysgro.2008.08.062
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Reduced pressure chemical vapor deposition of Ge thick layers on Si(001), Si(011) and Si(111)

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Cited by 82 publications
(88 citation statements)
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“…The thicker HT layer then provides a region in which any threading dislocation (TD) arms can glide and eliminate, thereby reducing their number reaching the surface of the buffer. The results of our work and of others [8][9][10][11] show that it is very challenging to grow smooth, high quality epitaxial layers compared to the (100) orientation. The main obstacle is the 4.2% lattice mismatch between Ge and Si.…”
Section: Introductionmentioning
confidence: 72%
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“…The thicker HT layer then provides a region in which any threading dislocation (TD) arms can glide and eliminate, thereby reducing their number reaching the surface of the buffer. The results of our work and of others [8][9][10][11] show that it is very challenging to grow smooth, high quality epitaxial layers compared to the (100) orientation. The main obstacle is the 4.2% lattice mismatch between Ge and Si.…”
Section: Introductionmentioning
confidence: 72%
“…12 Other techniques that have been tried include selective growth techniques such as aspect ratio trapping (ART) and epitaxial lateral overgrowth (ELO), 13,14 which is also quite common in III-V growth. 15 In previous reports of layers grown using the low temperature/high temperature technique, 10,11 thick LT layers were employed to allow for full relaxation and a smooth surface prior to HT layer growth. Research then focussed on details of the HT layers.…”
Section: Introductionmentioning
confidence: 99%
“…As the growth rate is extremely low (∼0.007 nm · s −1 ) at low temperature, a so-called low-temperature/high-temperature (LT/HT) two-step growth technique has been developed: [6][7][8][9] once a thin and flat Ge layer is formed at LT, Ge grows faster on the thin Ge template at HT. On the other hand, the growth rate of Si in SE method can be as high as 3.3 nm · s −1 at temperatures below 360…”
mentioning
confidence: 99%
“…integration with the existing silicon process technology and it has been a hot research topic for many years. [6][7][8][9] The main problem arises from the 4.2 % lattice mismatch (at 300K) between Ge and Si which ends up in misfit dislocations and other defects (e.g. twins).…”
Section: Introductionmentioning
confidence: 99%
“…twins). Indeed, using buffer layers and specific growth processes, high quality c-Ge can be epitaxially grown on Si using several growth steps involving temperatures above 600 • C. 10,8 However, low temperature deposition is useful for many applications. Among the benefits of low temperature epitaxy we would like to emphasize: i) the absence of thermal strain induced by differences in thermal expansion coefficients; ii) having a hydrogen terminated surface (less reactive), which is a key for low impurity incorporation in non UHV system; and iii) significant cost reduction thanks to well established low temperature plasma CVD reactors.…”
Section: Introductionmentioning
confidence: 99%