High pressurein situHCl etching of Si_1−xGe_xversus Si for advanced devices

Abstract

We have studied the gaseous hydrochloric acid selective etching of SiGe versus silicon in a reduced pressure-chemical vapor deposition reactor. Non-classical metal oxide semiconductor field effect transistors (MOSFETs) architectures, such as silicon on nothing (SON) and multi-bridge channels (MBC) devices require high SiGe:Si etch selectivities in order to get rid of the sacrificial SiGe layers. We have probed the in situ HCl etching of Si and SiGe blanket layers of SiGe/Si stacks grown selectively in the Si windows of patterned wafers ('SON-like' substrates) and of SiGe/Si superlattices ('MBC-like' substrates) as a function of the reverse absolute temperature. A switch from high temperature, diffusion-limited/low temperature, Cl-desorption-limited etch regimes to a unique LT regime, together with a significant etch rate increase, has been evidenced when drastically increasing the HCl partial pressure. Very good selectivities (versus Si) have been obtained when laterally etching high Ge content Si 1−x Ge x layers (typically 30%). A preferential etch by HCl of the {1 0 0} crystallographic planes compared to the {1 1 0} ones has been noticed both for the lateral etch of the 'SON-like' patterns (preferential etch of the pattern corners) and for the 'MBC-like' patterns (fullsheet (0 0 1) etch rates ≈10 times the {1 1 0} lateral etch rates). A slight etch rate difference between 'bottom-located' and 'top-located' Si 1−x Ge x layers in Si/SiGe superlattices has also been highlighted. This etching technique is thus usable for the processing of SON or MBC devices provided that the selective {1 0 0}:{1 1 0} HCl etch reported here is taken into account.

Low temperature boron and phosphorous doped SiGe for recessed and raised sources and drains

“…8. Given that the nominal blanket Si etch rate at 650 1C with a 180 Torr HCl partial pressure (180 Torr) is 0.8 nm/min [37], we should have removed 0.8-8 nm of the originally $ 10 nm thick Si S/D areas. We actually noticed that a Si 0.65 Ge 0.35 layer (same thickness than in Fig.…”

Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices

“…Of note are the double-gate [1], the localized silicon-on-insulator (L-SOI) [2], the silicon-on-nothing (SON) [3], the multi-channel (MC) [4,5] and the three-dimensional nano-wires (3D-NW) [6][7][8] devices. They all rely on (i) the (selective) epitaxy of SiGe/Si multilayers [9][10][11], (ii) the anisotropic etching of the active area [12] and (iii) the high degree of selectivity (versus Si) that can be achieved when laterally etching the SiGe layers (with Ge contents above 15%) [13][14][15][16][17]. In the L-SOI and SON approaches, the voids left by the removal of the SiGe buried layer are filled by a Si 3 N 4 /SiO 2 sandwich, leading to the formation of FETs (with localized buried dielectric layers beneath the Si surface channel/gate stacks) that electrically operate in a fully depleted-like regime.…”

(Invited) Cyclic Deposition/Etch Processes for the Formation of Si Raised Sources and Drains in Advanced MOSFETs

“…Second, we have shown in Ref. (15) that the etch rate of crystalline Si was roughly 10 times higher for high than for low HCl partial pressure (180 Torr versus 0.208 Torr). For a given Si thickness deposited during a CDE cycle, we should thus be able to significantly lower the process temperature while still keeping a reasonable throughput.…”