Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices

Hartmann, Jean‐Michel; Papon, Anne‐Marie; Barnes, Jean‐Paul; Billon, T.

doi:10.1016/j.jcrysgro.2009.03.027

Cited by 25 publications

(12 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…15) and (ii) the poly-SiGe(:B) growth rates associated with poly-crystalline layers grown on Si substrates covered by 100 nm of SiO 2 . 28 Full selectivity would be reached if the latter was equal to zero for some of the HCl mass-flows probed. This is very far from being the case.…”

Section: Is a Straightforward Selectivity Feasible By Adding Hcl To S...mentioning

confidence: 99%

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Hartmann

Benevent

André

et al. 2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (∼5 × 1020 cm−3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline and slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.

show abstract

Section: Is a Straightforward Selectivity Feasible By Adding Hcl To S...mentioning

confidence: 99%

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Hartmann

Benevent

André

et al. 2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…Interestingly, for the growth of Si and SiGe layers by CVD, the actual growth temperature on SOI is tendentially lower than for Si bulk substrates depending on the thickness of the device layer. [ 33 ] In our case, for MBE‐grown samples, the actual growth temperature is about 10 °C higher for SOI than for Si bulk, as can be seen by comparing Figure 3b (nominal

T_{normalG}

T_{normalA}

= 560 °C/550 °C,

θ_{Ge}

= 0.63 nm) with Figure 2c–e (

T_{normalG}

T_{normalA}

= 575 °C/565 °C – 565 °C/555 °C,

θ_{Ge}

= 0.62 nm). Also, for some CVD‐grown Si layers on SOI, an increased actual growth temperature was reported compared with Si bulk.…”

Section: Discussionmentioning

confidence: 99%

“…It is known from comparative studies using chemical vapor deposition (CVD) tools that the growth rates, and hence the growth temperatures of Si and SiGe layers, can vary between Si bulk and SOI substrates, [30][31][32] even up to %10 °C. [33] Moreover, even for the HWs grown on bulk Si substrates, there is no systematic study on the influence of the growth temperature on the HW growth. In the previous works, the growth temperature was kept constant, and the other parameters like annealing temperature and the annealing time were varied.…”

Section: Introductionmentioning

confidence: 99%

Epitaxial Growth of Planar Hutwires on Silicon‐on‐Insulator Substrates

Aberl

Vukušić

Fournel

et al. 2022

Physica Status Solidi (a)

View full text Add to dashboard Cite

Quantum devices based on holes confined in crystalline Ge nanostructures have emerged as a promising platform in the field of quantum technology. Epitaxial Ge hutwires (HWs) successfully used in pioneering quantum bit (qubit) experiments are the logical next choice for long‐distance coherent spin–spin coupling experiments. However, leakage currents are currently limiting the device performance of HWs on bulk Si substrates. This drawback can be mitigated by the HW growth on silicon‐on‐insulator (SOI) substrates. Herein, molecular beam epitaxy (MBE) HW growth developed on technologically relevant SOI substrates with different device layer thicknesses is shown. Using atomic force microscopy characterization, the fabrication of HWs on SOI with lengths of up to 600 nm is demonstrated. In addition, the very narrow window of growth parameters for which successful HW growth can be achieved and the distinct differences of HW growth on SOI versus bulk Si substrates are addressed.

show abstract

“…We have used a 200 mm Epi Centura reduced pressurechemical vapor deposition (RP-CVD) industrial cluster tool manufactured by Applied Materials to grow Ge and etch Si (using HCl) [21]. High purity hydrogen was used as the carrier gas.…”

Section: Methodsmentioning

confidence: 99%

Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

Destefanis

Hartmann

Baud

et al. 2010

Journal of Crystal Growth

Self Cite

View full text Add to dashboard Cite

Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices

Cited by 25 publications

References 23 publications

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Epitaxial Growth of Planar Hutwires on Silicon‐on‐Insulator Substrates

Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

Contact Info

Product

Resources

About