Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

Destefanis, V.; Hartmann, Jean‐Michel; Baud, L.; Delaye, V.; Billon, T.

doi:10.1016/j.jcrysgro.2010.01.003

Cited by 7 publications

(4 citation statements)

References 24 publications

(30 reference statements)

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“…several times the etched thickness during L-SOI(1 1 0) device fabrication, in order to magnify the effect). Such a roughening is discussed in more details in [26].…”

Section: Fabrication Of L-soi Devices On Patterned Si(1 0 0) and Si(1...mentioning

confidence: 95%

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Destefanis

Hartmann

Huguenin

et al. 2010

Semicond. Sci. Technol.

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The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 • C in windows of patterned wafers are rough, we have first of all studied the 600 • C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 • C down to 600 • C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 • C and 725 • C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 • C on (1 0 0) or at 600 • C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5-3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were notably obtained for the lateral etching of the (1 1 0) and (1 0 0) SiGe sacrificial layers (thanks to a CF 4 -based dry plasma), with no anisotropy. Significant hole mobility gains (electron mobility loss) compared to the universal Si(1 0 0)/SiO 2 mobility were evidenced in long, narrow (L = 10 μm; W = 0.08 μm) 'bulk-like' epitaxial Si(1 1 0) L-SOI devices (i.e. with SiGe still present under most of the Si channel). The gain (the loss) monotonically increased from 120% (11%) up to 246% (58%) when moving away from the [0 0 1] direction toward the [1 −1 0] direction (not reached, however: at most at 60 • to [0 0 1]). Vastly improved hole transport properties (a factor of 2 On current increase) were evidenced in short dimensions L-SOI devices (L = 0.35 μm; W = 0.08 μm) when switching from (1 0 0) surfaces with 1 1 0 conduction channels to (1 1 0) surfaces with a [0 0 1] propagation direction for the holes.

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“…several times the etched thickness during L-SOI(1 1 0) device fabrication, in order to magnify the effect). Such a roughening is discussed in more details in [26].…”

Section: Fabrication Of L-soi Devices On Patterned Si(1 0 0) and Si(1...mentioning

confidence: 95%

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Destefanis

Hartmann

Huguenin

et al. 2010

Semicond. Sci. Technol.

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“…Another method used to improve layer quality in molecular beam epitaxy (MBE) growth is to include Sb as a surfactant, but this can lead to significant dopant in the surface layers due to incorporation of the Sb. 12 Other techniques that have been tried include selective growth techniques such as aspect ratio trapping (ART) and epitaxial lateral overgrowth (ELO), 13,14 which is also quite common in III-V growth. 15 In previous reports of layers grown using the low temperature/high temperature technique, 10,11 thick LT layers were employed to allow for full relaxation and a smooth surface prior to HT layer growth.…”

Section: Introductionmentioning

confidence: 99%

High quality relaxed germanium layers grown on (110) and (111) silicon substrates with reduced stacking fault formation

Dobbie¹,

Myronov²,

Leadley³

2013

Journal of Applied Physics

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Epitaxial growth of Ge on Si has been investigated in order to produce high quality Ge layers on (110)- and (111)-orientated Si substrates, which are of considerable interest for their predicted superior electronic properties compared to (100) orientation. Using the low temperature/high temperature growth technique in reduced pressure chemical vapour deposition, high quality (111) Ge layers have been demonstrated almost entirely suppressing the formation of stacking faults (< 107 cm−2) with a very low rms roughness of less than 2 nm and a reduction in threading dislocation density (TDD) (∼ 3 × 108 cm−2). The leading factor in improving the buffer quality was use of a thin, partially relaxed Ge seed layer, where the residual compressive strain promotes an intermediate islanding step between the low temperature and high temperature growth phases. (110)-oriented layers were also examined and found to have similar low rms roughness (1.6 nm) and TDD below 108 cm−2, although use of a thin seed layer did not offer the same relative improvement seen for (111).

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“…Aspect ratio trapping, which is a technique for trapping threading dislocations in a limited Si region at SiO 2 trenches, has been expected to improve the crystallinity of Ge epitaxial films on a Si substrate. [13][14][15] In these reports, the selective growth of a Ge epitaxial layer has been demonstrated by chemical vapor deposition (CVD) with GeH 4 as a Ge precursor. [15][16][17][18] The CVD method is suitable for the selective epitaxial growth because the crystal growth by CVD is strongly dependent on the chemical state of the substrate surface.…”

Section: Introductionmentioning

confidence: 99%

Selective growth of Ge₁₋_xSn_xepitaxial layer on patterned SiO₂/Si substrate by metal–organic chemical vapor deposition

Takeuchi

Washizu

Ike

et al. 2017

Jpn. J. Appl. Phys.

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We have investigated the selective growth of a Ge 1%x Sn x epitaxial layer on a line/space-patterned SiO 2 /Si substrate by metal-organic chemical vapor deposition. We examined the behavior of a Sn precursor of tributyl(vinyl)tin (TBVSn) during the growth on Si and SiO 2 substrates and investigated the effect of the Sn precursor on the selective growth. The selective growth of the Ge 1%x Sn x epitaxial layer was performed under various total pressures and growth temperatures of 300 and 350 °C. The selective growth of the Ge 1%x Sn x epitaxial layer on the patterned Si region is achieved at a low total pressure without Ge 1%x Sn x growth on the SiO 2 region. In addition, we found that the Sn content in the Ge 1%x Sn x epitaxial layer increases with width of the SiO 2 region for a fixed Si width even with low total pressure. To control the Sn content in the selective growth of the Ge 1%x Sn x epitaxial layer, it is important to suppress the decomposition and migration of Sn and Ge precursors.

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Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

Cited by 7 publications

References 24 publications

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

High quality relaxed germanium layers grown on (110) and (111) silicon substrates with reduced stacking fault formation

Selective growth of Ge₁₋_xSn_xepitaxial layer on patterned SiO₂/Si substrate by metal–organic chemical vapor deposition

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Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

Cited by 7 publications

References 24 publications

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

High quality relaxed germanium layers grown on (110) and (111) silicon substrates with reduced stacking fault formation

Selective growth of Ge1−xSnxepitaxial layer on patterned SiO2/Si substrate by metal–organic chemical vapor deposition

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Selective growth of Ge₁₋_xSn_xepitaxial layer on patterned SiO₂/Si substrate by metal–organic chemical vapor deposition