(Invited) Cyclic Deposition/Etch Processes for the Formation of Si Raised Sources and Drains in Advanced MOSFETs

Abstract

We have studied the mechanisms underlying the Cyclic / Deposition Etch (CDE) of Si with either SiH 4 or SiH 2 Cl 2 + HCl for the deposition steps and HCl for the etch steps. We have first shown that the high partial pressure HCl etch rate of poly-Si was several times higher than the one of mono-crystalline Si (factor of 3-4 above 700°Cfactor of up to 15 at 600°C). We have then demonstrated that at 650°C, 300 Torr, SiH 4 / HCl CDE processes were selective versus SiO 2 provided that high numbers of cycles were used. We have then assessed the feasibility of growing rather thick Si 1-y C y layers at 600°C, 300 Torr thanks to SiH 4 and SiCH 6 (for a future used as stressors in devices with recessed Sources and Drains (S/D)). High growth pressures promoted the incorporation of C in substitutional rather than in interstitials sites, resulting in flat, rather high crystalline quality 30 nm thick Si 1-y C y layers with [C] subst. up to 1.3%. We have then showed that 20 Torr, SiH 2 Cl 2 + HCl -based CDE processes enabled to selectively grow 85 -140 nm thick, high crystalline quality intrinsic or in-situ doped Si Raised S/Ds on each side of multi-bridge channel Field Effect Transistors (FET) with Si 3 N 4 internal spacers (T = 750°C for Si and Si:B, T = 800°C for Si:Ph). Finally, we have demonstrated the efficiency of 1 and 6 cycles CDE process (instead of a unique growth step) in suppressing mushrooming on top of un-capped poly-Si gates of Fully Depleted Silicon-On-Insulator FETs after the formation of Si RSD. {116}-{117} facets at the boundary between the gate stack and the S/D regions together with moat recess at the edges of active regions were however associated to our CDE processes.

Disilane-based cyclic deposition/etch of Si, Si:P and Si1−yCy:P layers: I. The elementary process steps

“…The repetition of growth and etch steps (hence the 'cyclic deposition/etch' name) yields the desired active layer thickness, with full selectivity (see figure 1 schematics inspired from [8]). CDE is usually conducted at low temperatures ( 600 • C) for several practical reasons: (i) as far as Si 1−y C y :P 0268-1242/13/025017+10$33.00 layers are concerned, the lower the temperature and the higher the growth rate, the higher the substitutional C content in those layers [9,10]; (ii) high Ge content SiGe:B layers as in [11] will remain fully compressively strained and (iii) amorphous layers deposited at low temperatures on dielectrics will be etched much faster (compared to mono-crystalline layers) than higher temperature poly-crystalline layers [7,12].…”

Low Temperature Cyclic Deposition/Etch (CDE) of Tensile-Strained Si:P

“…This was not a given and should be useful on patterned wafers (as less materials on dielectrics will have to be removed, then). We for instance had twice thicker poly-Si films on SiO2 than Si films on Si active areas with a 650°C, 20 Torr CDE process based on SiH4 and HCl (12). Based on Fig.…”

Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

“…Compared with the conventional etch process, the multi-cycle etch process delivers an excellent control of spacer pull-back loading for an universal pattern density area (Fig. To avoid the poly-Si mushrooms defect on the top of unprotected or imperfectly protected gates for FinFETs, a good SIN hard mask protection and the high selectivity Si 1-x Ge x growth on silicon vs. SiO2 (the isolation) and SIN (the sidewall spacers) are both necessary (10). However, there is a trade-off between the SIN capping layer protection and the SIN spacer pull-back at the S/D fin recess steps.…”