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We have benchmarked the 550 • C, 20 Torr growth of Si:P and Si 1−y C y :P using SiH 4 and Si 2 H 6 . P segregation has prevented us from reaching P + ion concentrations in Si higher than a few 10 19 cm −3 using SiH 4 ; the resulting surface 'poisoning' led to a severe growth rate reduction. Meanwhile, [P + ] increased linearly with the phosphine flow when using Si 2 H 6 as the Si precursor; values as high as 1.7 × 10 20 cm −3 were obtained. The Si:P growth rate using Si 2 H 6 was initially stable then increased as the PH 3 flow increased. Mono-methylsilane flows 6.5-10 times higher were needed with Si 2 H 6 than with SiH 4 to reach the same substitutional C concentrations in intrinsic Si 1−y C y layers ([C] subst. up to 1.9%). Growth rates were approximately six times higher with Si 2 H 6 than with SiH 4 , however. 30 nm thick Si 1−y C y layers became rough as [C] subst. exceeded 1.6% (formation of increasing numbers of islands). We have also studied the structural and electrical properties of 'low' and 'high' C content Si 1−y C y :P layers (∼ 1.5 and 1.8%, respectively) grown with Si 2 H 6 . Adding significant amounts of PH 3 led to a reduction of the tensile strain in the films. This was due to the incorporation of P atoms (at the expense of C atoms) in the substitutional sites of the Si matrix. Si 1−y C y :P layers otherwise became rough as the PH 3 flow increased. Resistivities lower than 1 m cm were nevertheless associated with those Si 1−y C y :P layers, with P atomic concentrations at most 3.9 × 10 20 cm −3 . Finally, we have quantified the beneficial impact of adding GeH 4 to HCl for the low-temperature etching of Si. Etch rates 12-36 times higher with HCl + GeH 4 than with pure HCl were achieved at 20 Torr. Workable etch rates close to 1 nm min −1 were obtained at 600 • C (versus 750 • C for pure HCl), enabling low-temperature cyclic deposition/etch strategies for the selective epitaxial growth of Si, Si:P and Si 1−y C y :P layers on patterned wafers.

the latter and to achieve extremely high packing density. [9] The understanding of switching mechanisms at device level is a key factor for a technology to be viable at very large scale integration. Different types of resistive memory devices have been studied in the past years such as oxide-based memories (OxRAM) and conductive bridge random access memories (CBRAM). It should be noted that for both technologies it is very challenging to combine good cycling endurance, stable retention and high window margin (WM). Two distinct resistive states can be obtained based on a reversible filament formation (SET operation) and rupture (RESET operation) inside an insulating layer sandwiched between two electrodes; SET operation being the switching from a high resistive state (HRS) to a low resistive state (LRS) and RESET the reverse operation (HRS to LRS). In the case of CBRAM, metal ions coming from top electrode (TE) are introduced in the insulating layer. Working principle is based on a metallic filament formation and dissolution controlling performances. [10] These devices present high WM, relatively low endurance, and poor retention stability. [11,12] In the case of OxRAM, oxygen vacancies creation and annihilation inside the oxide dominates the switching mechanism. [13][14][15] This technology shows low WM combined to high endurance and stable retention. [3,16] While lots of effort have been done lately to improve switching speed and power consumption in RRAM, [17,18] several challenges need to be overcome, namely the high extrinsic (device to device) and intrinsic (cycle to cycle) variability in RRAM characteristics. [7] High WM could potentially help solving this variability by maximizing the ratio of HRS over LRS. Moreover, coupling high WM and high endurance (up to 10 8 cycles required for storage class applications [19] ) remains a critical issue. Combining CBRAM and OxRAM in one hybrid oxide-based CBRAM (hybrid-RRAM (HRRAM)) where filament can be composed of metal ions and oxygen vacancies could offer alternative performances such as high WM coupled with high endurance. Recent studies have identified materials issues in oxide and metal based RRAM. [20,21] However, material properties study is still lacking in HRRAM to guide stack choice (oxide vs electrodes) toward a given application. In a previous work, a trade-off between endurance, window margin, and retention was demonstrated. When comparing various HRRAM electrical performances and filament composition, Here, the impact of copper and oxygen vacancy balance in filament composition as a key factor for oxide-based conductive bridge random access memories (hybrid resistive random access memories (HRRAMs)) performances is investigated. To this aim, several RRAM technologies are studied using various resistive layers and top electrodes. Material analyses allow to highlight the hybrid aspect of HRRAM conductive filament. Density functional theory simulations are used to extract microscopic features and highlight differences from a material point of view. Integr...

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K. Szeto from C2P2-LCOMS. ETH Zürich, CPE Lyon and UCBL are also acknowledged for their scientific support and the access to the process and characterization facilities. ASSOCIATED CONTENT Supporting Information. Experimental and computational details; in-situ IR and solid-state NMR spectra are available free of charge on the ACS Publications website.

Designing new approaches to incorporate dopant impurities in semiconductor materials is essential in keeping pace with electronics miniaturization without device performance degradation. On the basis of a mild solution-phase synthetic approach to functionalize silica nanoparticles, we were able to graft tailor-made boronmolecular precursors and control the thermal release of boron in the silica framework. The molecular-level description of the surface structure lays the foundation for a structure−property relationship approach, which is readily and successfully implemented to dope non-deglazed silicon wafers. As the method does not require an additional oxide capping step and shows minimal risk of carbon contamination, as demonstrated by compositional and electrical characterizations of the wafers, it is perfectly adapted to advanced microelectronics manufacturing processes. ■ INTRODUCTIONDopants play a critical role in semiconductor devices and are therefore a major focus of research. 1−3 For instance, several doping strategies have emerged and led to significant improvements to drive impurities (dopant) inside pure substrates and to reduce the variability of targeted electronic devices, together with increased performances for nanoobjects. 4−11 However, improving dopant incorporation, avoiding randomness of concentration, and investigating diffusion phenomena still represent an outstanding challenge today, in particular with the development of smaller nanosized devices. 8 Indeed, increasing the performance in microelectronics has been directly related to the continuing shrinking of transistors 12 and thus to their optimized properties. The control of dopant concentration and distribution in semiconductors is essential, 8 and several methods such as single-ion implantation, 6 chemisorption of dopant from gaseous hydride molecules, 9,10 spin-on doping, 11 or single-atom doping 13 have been investigated. The monolayer doping (MLD) concept 14 appeared to be well-adapted to the medium doping range targeted for transistors or junctions in Fins as well as in nanowire structures. 15,16 However, transferring this process to the microelectronic industry is difficult because it requires a rather nonmanufacturing-friendly substrate (hydrofluoric acid deglazed silicon) and the use of a low-temperature, conformal SiO 2 evaporation capping to avoid dopant evaporation upon annealing. To circumvent this capping issue, the monolayer contact doping (MLCD) concept was recently proposed. 17,18 While providing good results in the formation of (ultra)shallow junctions, the use of two substrates (donor and acceptor) makes this ex situ technique not as straightforward as approaches related to MLD, relying on only one substrate.In this work, we show how to avoid these issues by the use of a simple bottom-up methodology based on the grafting of tailored boron-containing molecular precursors (anchoring/ self-protected) on the thin layer of native silica present on top of silicon wafers. This method takes advantage of (i) the presence of a...

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