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The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power splitter features good impedance match at all ports without the insertion losses being inherent to common resistive power splitters. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate above 3.5 Gbps.

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplicationand-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations. Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor. The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors. Index Terms-Application specific integrated circuits (ASIC's), carry save adders, COordinate Rotation DIgital Computer (CORDIC), fast Fourier transform (FFT), full-custom, gallium arsenide (GaAs) VLSI design, high-performance systems. at the same university. He has published five edited books, over 30 journal papers, and 70 conference papers. His current research fields include GaAs technology (circuit, logic, and module design, RISC and DSP processor core designs, telecom IC designs, GaAs ASIC synthesis, and GaAs full custom compilation), VLSI microarchitectures (advanced digital signal processor and application specific integrated processors), and optimization of digital integrated circuits (including routing and layout techniques, power estimation, timing, and interconnect analysis).

In a short period of time, the multimedia sector has quickly progressed trying to overcome the exigencies of the customers in terms of transfer speeds, storage memory, image quality, and functionalities. In order to cope with this stringent situation, different hardware devices have been developed as possible choices. Despite of the fact that not every device is apt for implementing the high computational demands associated to multimedia applications; reconfigurable architectures appear as ideal candidates to achieve these necessities. As a direct consequence, worldwide universities and industries have incremented their research activity into this area, generating an important know-how base. In order to sort all the information generated about this issue, this paper reviews the most recent reconfigurable architectures for multimedia applications. As a result, this paper establishes the benefits and drawbacks of the different dynamically reconfigurable architectures for multimedia applications according to their system-level design.

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