Low Cost Efficient Architecture for H.264 Motion Estimation

López, Sebastián; Tobajas, F.; Villar, Aitor; Armas, V. de; Lopez, J.F.; Sarmiento, Roberto

doi:10.1109/iscas.2005.1464612

Cited by 13 publications

(10 citation statements)

References 8 publications

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“…The proposed approach is very cost efficient and can be used in the design of [5,6,7, 12] VBSME engines. As a case study, this approach is used to design a one-dimensional (1-D) systolic array VBSME architecture for H.264/AVC.…”

Section: Motivation and Contributionmentioning

confidence: 99%

“…In this work, we focus on 1-D arrays. 2-D arrays, such as the one by Kim et al [5] are beyond the scope of this work.…”

Section: Related Workmentioning

confidence: 99%

“…Wei and Gang [10] built a 1D systolic array VBSME architecture, similar to those described above, with 16 PEs, a 4-stage adder tree, and two flexible (16×16 bit) 8-bit register arrays. López et al [5] designed a similar 1D array using SRAMs to implement the RUs shown in Fig. 2(b).…”

Section: Related Workmentioning

confidence: 99%

“…The architectures of Li and Leong [4] and López et al [5] were synthesized on Virtex 2 series FPGAs. Table 2 shows a comparison between our architecture, also synthesized on a Virtex 2, and both of these.…”

Section: Fpga Implementationmentioning

confidence: 99%

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Scalable and low cost design approach for variable block size motion estimation (VBSME)

Parandeh-Afshar

Brisk

Ienne

2009

2009 International Symposium on VLSI Design, Automation and Test

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Variable block size motion estimation (VBSME) in state-of-theart video coding standards is one of the key features which improves the coding efficiency significantly compared to the previous standards. VBSME hardware design is a challenging task due to its complexity. The processing power requirement for VBSME depends on many factors such as frame size, frame rate and search area. In video coding standards these features are allowed to vary, depending on the requirements of the application. In this paper, a scalable and low cost approach is proposed for designing the VBSME which allows us to tailor the architecture for different applications requirements and implementation targets efficiently. This approach can be used in redesigning of current VBSME architectures to improve their scalability and reduce their design costs. Moreover, as this technique is not block size dependent, it can be employed in designing future coding standards with different block sizes.

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Section: Motivation and Contributionmentioning

confidence: 99%

“…In this work, we focus on 1-D arrays. 2-D arrays, such as the one by Kim et al [5] are beyond the scope of this work.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Fpga Implementationmentioning

confidence: 99%

See 2 more Smart Citations

Scalable and low cost design approach for variable block size motion estimation (VBSME)

Parandeh-Afshar

Brisk

Ienne

2009

2009 International Symposium on VLSI Design, Automation and Test

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“…Of previously reported FPGA implementations [9][10][11][12][13][14][15][16], only two [15,16] support VBS-ME, and both are bit-parallel. A most significant bit (MSB)-first bit-serial design with early termination was proposed for QCIF resolution video [13] which employed a FS within the range −15 to +16.…”

Section: Introductionmentioning

confidence: 99%

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

Leong

2007

J Sign Process Syst Sign Image

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H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bitserial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.

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A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

et al. 2015

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International audienceImage and video processing applications represent major challenge concerning real-time embedded systems. In video coding, adjacent frames are similar; this correlation can be exploited to reduce the amount of data to be transmitted, in this case reducing temporal redundancies. Actually, H.264/AVC is the most popular standard; the high performance that offers magnifies the difficulty of a real-time implementation. This complexity is mainly related to the operation of the motion estimation and requires high computational power. This paper presents an efficient hardware implementation of integer motion estimation for H.264/AVC encoder. The considered methodology is based on full search block matching algorithm for its regular algorithm implementation. The proposed architecture enables variable block size motion estimation and computes 41 motion vectors values (MVs) resulted from each 16 × 16 bloc and its derived sub-blocks. The proposed architecture calculates the best MV using a parallel process composed of three processor modules and a set of comparators three values. Implementation results based on field-programmable gate arrays devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency reduced up to 80 %, high processing speed reaching 443 MHz of frequency. The processing capacity is up to 1920 × 1088 HD video streams with a search range of 48 × 48

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Low Cost Efficient Architecture for H.264 Motion Estimation

Cited by 13 publications

References 8 publications

Scalable and low cost design approach for variable block size motion estimation (VBSME)

Scalable and low cost design approach for variable block size motion estimation (VBSME)

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

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