Scalable and low cost design approach for variable block size motion estimation (VBSME)

Parandeh-Afshar, Hadi; Brisk, Philip; Ienne, Paolo

doi:10.1109/vdat.2009.5158147

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…Gate count of López et al [6] architecture is comparable with proposed architecture but it offers frame rate of only 60 fps for CIF resolution which in actuality is very less. Gate count of [15] is lesser compared to proposed design but frame processing rate is not given and therefore is not adequate for comparison. Architecture presented by Olivares [12] can process 21.42 HD (1920 × 1080) resolution frames with 256 PEs; still this frame rate is not sufficient for real time implementation.…”

Section: Synthesis Results Ofmentioning

confidence: 95%

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Shah¹,

Singapuri

Dalal

2016

Journal of Electrical and Computer Engineering

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Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.

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Section: Synthesis Results Ofmentioning

confidence: 95%

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Shah¹,

Singapuri

Dalal

2016

Journal of Electrical and Computer Engineering

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“…But the function of the ALU and the size of the local PE memory are not enough for recent complicated visual application. Reference [7] proposes VBMSE architecture to compute the motion estimation vector of a video frame for the H.264/AVC. This architecture is composed of a systolic array of regular data processing elements (PE).…”

Section: Related Workmentioning

confidence: 99%

“…The RC Array functionality and interconnection network are configured through 32-bit context words. The [7] and [8] reference architectures are more efficient than [6] architecture but their PE design is targeted to the desired application. This method of conception usually responses to the required performance but faces the problem of difficulty and a long time of conception as well as a limitation of utilization for a specific application.…”

Section: Related Workmentioning

confidence: 99%

Soft-core reduction methodology for SIMD architecture: OPENRISC case study

Dammak

Baklouti

Abid

2010

2010 5th International Design and Test Workshop

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Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.I.

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“…-Circuits Naturally Containing Adder/Compressor Trees. This class contains three circuits: 3-and 6-tap FIR filters (fir3, fir6), and one processing element of a variable block size motion estimator for H.264 video coding (H.264 ME) [Parandeh-Afshar et al 2009]. These circuits are naturally written with compressor trees or all CPAs clustered together to form adder trees.…”

Section: Benchmarksmentioning

confidence: 99%

Field Programmable Compressor Trees

Cevrero

Athanasopoulos

Parandeh-Afshar

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition; however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable Compressor Tree (FPCT) as an alternative to the DSP blocks. By providing just a compressor tree, the FPCT can perform multi-input addition along with parallel multiplication and MAC in conjunction with a small amount of FPGA general logic. Furthermore, the user can configure the FPCT to precisely match the bitwidths of the operands being summed. Although an FPCT cannot beat the performance of a well-designed ASIC compressor tree of fixed bitwidth, for example, 9×9 and 18×18-bit multipliers/MACs in DSP blocks, its configurable bitwidth and

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Scalable and low cost design approach for variable block size motion estimation (VBSME)

Cited by 5 publications

References 14 publications

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Soft-core reduction methodology for SIMD architecture: OPENRISC case study

Field Programmable Compressor Trees

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